34fef0c980
Summary: Add CVTSQ/CVTDQ/CVTQD/CVTQS instructions. Add regression tests for them and other convert instructions of asmparser, mccodeemitter, and disassembler. In order to add those instructions, support RD operands in asmparser, mccodeemitter, and disassembler. Differential Revision: https://reviews.llvm.org/D81536
357 lines
8.8 KiB
C++
357 lines
8.8 KiB
C++
//===-- VE.h - Top-level interface for VE representation --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// VE back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_VE_VE_H
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#define LLVM_LIB_TARGET_VE_VE_H
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#include "MCTargetDesc/VEMCTargetDesc.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class FunctionPass;
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class VETargetMachine;
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class formatted_raw_ostream;
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class AsmPrinter;
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class MCInst;
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class MachineInstr;
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FunctionPass *createVEISelDag(VETargetMachine &TM);
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FunctionPass *createVEPromoteToI1Pass();
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void LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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AsmPrinter &AP);
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} // namespace llvm
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namespace llvm {
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// Enums corresponding to VE condition codes, both icc's and fcc's. These
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// values must be kept in sync with the ones in the .td file.
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namespace VECC {
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enum CondCode {
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// Integer comparison
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CC_IG = 0, // Greater
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CC_IL = 1, // Less
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CC_INE = 2, // Not Equal
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CC_IEQ = 3, // Equal
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CC_IGE = 4, // Greater or Equal
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CC_ILE = 5, // Less or Equal
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// Floating point comparison
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CC_AF = 0 + 6, // Never
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CC_G = 1 + 6, // Greater
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CC_L = 2 + 6, // Less
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CC_NE = 3 + 6, // Not Equal
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CC_EQ = 4 + 6, // Equal
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CC_GE = 5 + 6, // Greater or Equal
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CC_LE = 6 + 6, // Less or Equal
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CC_NUM = 7 + 6, // Number
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CC_NAN = 8 + 6, // NaN
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CC_GNAN = 9 + 6, // Greater or NaN
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CC_LNAN = 10 + 6, // Less or NaN
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CC_NENAN = 11 + 6, // Not Equal or NaN
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CC_EQNAN = 12 + 6, // Equal or NaN
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CC_GENAN = 13 + 6, // Greater or Equal or NaN
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CC_LENAN = 14 + 6, // Less or Equal or NaN
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CC_AT = 15 + 6, // Always
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UNKNOWN
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};
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}
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// Enums corresponding to VE Rounding Mode. These values must be kept in
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// sync with the ones in the .td file.
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namespace VERD {
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enum RoundingMode {
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RD_NONE = 0, // According to PSW
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RD_RZ = 8, // Round toward Zero
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RD_RP = 9, // Round toward Plus infinity
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RD_RM = 10, // Round toward Minus infinity
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RD_RN = 11, // Round to Nearest (ties to Even)
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RD_RA = 12, // Round to Nearest (ties to Away)
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UNKNOWN
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};
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}
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inline static const char *VECondCodeToString(VECC::CondCode CC) {
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switch (CC) {
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case VECC::CC_IG: return "gt";
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case VECC::CC_IL: return "lt";
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case VECC::CC_INE: return "ne";
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case VECC::CC_IEQ: return "eq";
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case VECC::CC_IGE: return "ge";
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case VECC::CC_ILE: return "le";
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case VECC::CC_AF: return "af";
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case VECC::CC_G: return "gt";
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case VECC::CC_L: return "lt";
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case VECC::CC_NE: return "ne";
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case VECC::CC_EQ: return "eq";
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case VECC::CC_GE: return "ge";
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case VECC::CC_LE: return "le";
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case VECC::CC_NUM: return "num";
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case VECC::CC_NAN: return "nan";
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case VECC::CC_GNAN: return "gtnan";
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case VECC::CC_LNAN: return "ltnan";
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case VECC::CC_NENAN: return "nenan";
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case VECC::CC_EQNAN: return "eqnan";
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case VECC::CC_GENAN: return "genan";
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case VECC::CC_LENAN: return "lenan";
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case VECC::CC_AT: return "at";
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default:
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llvm_unreachable("Invalid cond code");
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}
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}
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inline static VECC::CondCode stringToVEICondCode(StringRef S) {
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return StringSwitch<VECC::CondCode>(S)
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.Case("gt", VECC::CC_IG)
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.Case("lt", VECC::CC_IL)
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.Case("ne", VECC::CC_INE)
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.Case("eq", VECC::CC_IEQ)
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.Case("ge", VECC::CC_IGE)
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.Case("le", VECC::CC_ILE)
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.Case("af", VECC::CC_AF)
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.Case("at", VECC::CC_AT)
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.Case("", VECC::CC_AT)
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.Default(VECC::UNKNOWN);
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}
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inline static VECC::CondCode stringToVEFCondCode(StringRef S) {
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return StringSwitch<VECC::CondCode>(S)
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.Case("gt", VECC::CC_G)
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.Case("lt", VECC::CC_L)
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.Case("ne", VECC::CC_NE)
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.Case("eq", VECC::CC_EQ)
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.Case("ge", VECC::CC_GE)
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.Case("le", VECC::CC_LE)
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.Case("num", VECC::CC_NUM)
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.Case("nan", VECC::CC_NAN)
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.Case("gtnan", VECC::CC_GNAN)
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.Case("ltnan", VECC::CC_LNAN)
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.Case("nenan", VECC::CC_NENAN)
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.Case("eqnan", VECC::CC_EQNAN)
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.Case("genan", VECC::CC_GENAN)
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.Case("lenan", VECC::CC_LENAN)
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.Case("af", VECC::CC_AF)
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.Case("at", VECC::CC_AT)
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.Case("", VECC::CC_AT)
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.Default(VECC::UNKNOWN);
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}
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inline static unsigned VECondCodeToVal(VECC::CondCode CC) {
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switch (CC) {
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case VECC::CC_IG:
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return 1;
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case VECC::CC_IL:
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return 2;
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case VECC::CC_INE:
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return 3;
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case VECC::CC_IEQ:
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return 4;
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case VECC::CC_IGE:
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return 5;
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case VECC::CC_ILE:
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return 6;
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case VECC::CC_AF:
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return 0;
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case VECC::CC_G:
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return 1;
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case VECC::CC_L:
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return 2;
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case VECC::CC_NE:
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return 3;
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case VECC::CC_EQ:
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return 4;
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case VECC::CC_GE:
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return 5;
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case VECC::CC_LE:
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return 6;
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case VECC::CC_NUM:
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return 7;
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case VECC::CC_NAN:
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return 8;
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case VECC::CC_GNAN:
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return 9;
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case VECC::CC_LNAN:
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return 10;
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case VECC::CC_NENAN:
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return 11;
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case VECC::CC_EQNAN:
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return 12;
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case VECC::CC_GENAN:
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return 13;
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case VECC::CC_LENAN:
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return 14;
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case VECC::CC_AT:
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return 15;
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default:
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llvm_unreachable("Invalid cond code");
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}
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}
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inline static VECC::CondCode VEValToCondCode(unsigned Val, bool IsInteger) {
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if (IsInteger) {
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switch (Val) {
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case 0:
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return VECC::CC_AF;
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case 1:
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return VECC::CC_IG;
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case 2:
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return VECC::CC_IL;
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case 3:
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return VECC::CC_INE;
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case 4:
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return VECC::CC_IEQ;
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case 5:
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return VECC::CC_IGE;
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case 6:
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return VECC::CC_ILE;
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case 15:
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return VECC::CC_AT;
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}
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} else {
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switch (Val) {
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case 0:
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return VECC::CC_AF;
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case 1:
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return VECC::CC_G;
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case 2:
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return VECC::CC_L;
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case 3:
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return VECC::CC_NE;
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case 4:
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return VECC::CC_EQ;
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case 5:
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return VECC::CC_GE;
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case 6:
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return VECC::CC_LE;
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case 7:
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return VECC::CC_NUM;
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case 8:
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return VECC::CC_NAN;
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case 9:
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return VECC::CC_GNAN;
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case 10:
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return VECC::CC_LNAN;
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case 11:
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return VECC::CC_NENAN;
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case 12:
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return VECC::CC_EQNAN;
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case 13:
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return VECC::CC_GENAN;
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case 14:
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return VECC::CC_LENAN;
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case 15:
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return VECC::CC_AT;
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}
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}
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llvm_unreachable("Invalid cond code");
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}
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inline static const char *VERDToString(VERD::RoundingMode R) {
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switch (R) {
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case VERD::RD_NONE:
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return "";
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case VERD::RD_RZ:
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return ".rz";
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case VERD::RD_RP:
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return ".rp";
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case VERD::RD_RM:
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return ".rm";
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case VERD::RD_RN:
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return ".rn";
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case VERD::RD_RA:
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return ".ra";
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default:
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llvm_unreachable("Invalid branch predicate");
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}
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}
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inline static VERD::RoundingMode stringToVERD(StringRef S) {
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return StringSwitch<VERD::RoundingMode>(S)
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.Case("", VERD::RD_NONE)
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.Case(".rz", VERD::RD_RZ)
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.Case(".rp", VERD::RD_RP)
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.Case(".rm", VERD::RD_RM)
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.Case(".rn", VERD::RD_RN)
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.Case(".ra", VERD::RD_RA)
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.Default(VERD::UNKNOWN);
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}
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inline static unsigned VERDToVal(VERD::RoundingMode R) {
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switch (R) {
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case VERD::RD_NONE:
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case VERD::RD_RZ:
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case VERD::RD_RP:
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case VERD::RD_RM:
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case VERD::RD_RN:
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case VERD::RD_RA:
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return static_cast<unsigned>(R);
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default:
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break;
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}
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llvm_unreachable("Invalid branch predicates");
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}
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inline static VERD::RoundingMode VEValToRD(unsigned Val) {
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switch (Val) {
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case static_cast<unsigned>(VERD::RD_NONE):
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return VERD::RD_NONE;
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case static_cast<unsigned>(VERD::RD_RZ):
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return VERD::RD_RZ;
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case static_cast<unsigned>(VERD::RD_RP):
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return VERD::RD_RP;
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case static_cast<unsigned>(VERD::RD_RM):
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return VERD::RD_RM;
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case static_cast<unsigned>(VERD::RD_RN):
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return VERD::RD_RN;
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case static_cast<unsigned>(VERD::RD_RA):
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return VERD::RD_RA;
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default:
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break;
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}
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llvm_unreachable("Invalid branch predicates");
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}
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// MImm - Special immediate value of sequential bit stream of 0 or 1.
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// See VEInstrInfo.td for details.
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inline static bool isMImmVal(uint64_t Val) {
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if (Val == 0) {
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// (0)1 is 0
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return true;
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}
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if (isMask_64(Val)) {
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// (m)0 patterns
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return true;
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}
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// (m)1 patterns
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return (Val & (1UL << 63)) && isShiftedMask_64(Val);
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}
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inline static bool isMImm32Val(uint32_t Val) {
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if (Val == 0) {
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// (0)1 is 0
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return true;
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}
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if (isMask_32(Val)) {
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// (m)0 patterns
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return true;
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}
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// (m)1 patterns
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return (Val & (1 << 31)) && isShiftedMask_32(Val);
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}
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inline unsigned M0(unsigned Val) { return Val + 64; }
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inline unsigned M1(unsigned Val) { return Val; }
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} // namespace llvm
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#endif
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