819b2d9c79
When diffing disassembly dump of two binaries, I see lots of noises from mismatched jump target addresses and global data references, which unnecessarily causes diffs on every function, making it impractical. I'm trying to symbolize the raw binary addresses to minimize the diff noise.
In this change, a local branch target is modeled as a label and the branch target operand will simply be printed as a label. Local labels are collected by a separate pre-decoding pass beforehand. A global data memory operand will be printed as a global symbol instead of the raw data address. Unfortunately, due to the way the disassembler is set up and to be less intrusive, a global symbol is always printed as the last operand of a memory access instruction. This is less than ideal but is probably acceptable from checking code quality point of view since on most targets an instruction can have at most one memory operand.
So far only the X86 disassemblers are supported.
Test Plan:
llvm-objdump -d --x86-asm-syntax=intel --no-show-raw-insn --no-leading-addr :
```
Disassembly of section .text:
<_start>:
push rax
mov dword ptr [rsp + 4], 0
mov dword ptr [rsp], 0
mov eax, dword ptr [rsp]
cmp eax, dword ptr [rip + 4112] # 202182 <g>
jge 0x20117e <_start+0x25>
call 0x201158 <foo>
inc dword ptr [rsp]
jmp 0x201169 <_start+0x10>
xor eax, eax
pop rcx
ret
```
llvm-objdump -d **--symbolize-operands** --x86-asm-syntax=intel --no-show-raw-insn --no-leading-addr :
```
Disassembly of section .text:
<_start>:
push rax
mov dword ptr [rsp + 4], 0
mov dword ptr [rsp], 0
<L1>:
mov eax, dword ptr [rsp]
cmp eax, dword ptr <g>
jge <L0>
call <foo>
inc dword ptr [rsp]
jmp <L1>
<L0>:
xor eax, eax
pop rcx
ret
```
Note that the jump instructions like `jge 0x20117e <_start+0x25>` without this work is printed as a real target address and an offset from the leading symbol. With a change in the optimizer that adds/deletes an instruction, the address and offset may shift for targets placed after the instruction. This will be a problem when diffing the disassembly from two optimizers where there are unnecessary false positives due to such branch target address changes. With `--symbolize-operand`, a label is printed for a branch target instead to reduce the false positives. Similarly, the disassemble of PC-relative global variable references is also prone to instruction insertion/deletion.
Reviewed By: jhenderson, MaskRay
Differential Revision: https://reviews.llvm.org/D84191
499 lines
18 KiB
C++
499 lines
18 KiB
C++
//===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file includes code for rendering MCInst instances as AT&T-style
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// assembly.
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//
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//===----------------------------------------------------------------------===//
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#include "X86ATTInstPrinter.h"
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#include "X86BaseInfo.h"
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#include "X86InstComments.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Format.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cinttypes>
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#include <cstdint>
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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// Include the auto-generated portion of the assembly writer.
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#define PRINT_ALIAS_INSTR
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#include "X86GenAsmWriter.inc"
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void X86ATTInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << markup("<reg:") << '%' << getRegisterName(RegNo) << markup(">");
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}
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void X86ATTInstPrinter::printInst(const MCInst *MI, uint64_t Address,
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StringRef Annot, const MCSubtargetInfo &STI,
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raw_ostream &OS) {
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// If verbose assembly is enabled, we can print some informative comments.
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if (CommentStream)
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HasCustomInstComment = EmitAnyX86InstComments(MI, *CommentStream, MII);
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printInstFlags(MI, OS);
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// Output CALLpcrel32 as "callq" in 64-bit mode.
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// In Intel annotation it's always emitted as "call".
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//
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// TODO: Probably this hack should be redesigned via InstAlias in
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// InstrInfo.td as soon as Requires clause is supported properly
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// for InstAlias.
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if (MI->getOpcode() == X86::CALLpcrel32 &&
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(STI.getFeatureBits()[X86::Mode64Bit])) {
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OS << "\tcallq\t";
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printPCRelImm(MI, Address, 0, OS);
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}
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// data16 and data32 both have the same encoding of 0x66. While data32 is
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// valid only in 16 bit systems, data16 is valid in the rest.
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// There seems to be some lack of support of the Requires clause that causes
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// 0x66 to be interpreted as "data16" by the asm printer.
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// Thus we add an adjustment here in order to print the "right" instruction.
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else if (MI->getOpcode() == X86::DATA16_PREFIX &&
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STI.getFeatureBits()[X86::Mode16Bit]) {
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OS << "\tdata32";
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}
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// Try to print any aliases first.
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else if (!printAliasInstr(MI, Address, OS) && !printVecCompareInstr(MI, OS))
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printInstruction(MI, Address, OS);
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// Next always print the annotation.
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printAnnotation(OS, Annot);
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}
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bool X86ATTInstPrinter::printVecCompareInstr(const MCInst *MI,
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raw_ostream &OS) {
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if (MI->getNumOperands() == 0 ||
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!MI->getOperand(MI->getNumOperands() - 1).isImm())
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return false;
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int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
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const MCInstrDesc &Desc = MII.get(MI->getOpcode());
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// Custom print the vector compare instructions to get the immediate
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// translated into the mnemonic.
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switch (MI->getOpcode()) {
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case X86::CMPPDrmi: case X86::CMPPDrri:
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case X86::CMPPSrmi: case X86::CMPPSrri:
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case X86::CMPSDrm: case X86::CMPSDrr:
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case X86::CMPSDrm_Int: case X86::CMPSDrr_Int:
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case X86::CMPSSrm: case X86::CMPSSrr:
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case X86::CMPSSrm_Int: case X86::CMPSSrr_Int:
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if (Imm >= 0 && Imm <= 7) {
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OS << '\t';
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printCMPMnemonic(MI, /*IsVCMP*/false, OS);
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if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
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if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
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printdwordmem(MI, 2, OS);
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else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
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printqwordmem(MI, 2, OS);
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else
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printxmmwordmem(MI, 2, OS);
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} else
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printOperand(MI, 2, OS);
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// Skip operand 1 as its tied to the dest.
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OS << ", ";
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printOperand(MI, 0, OS);
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return true;
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}
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break;
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case X86::VCMPPDrmi: case X86::VCMPPDrri:
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case X86::VCMPPDYrmi: case X86::VCMPPDYrri:
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case X86::VCMPPDZ128rmi: case X86::VCMPPDZ128rri:
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case X86::VCMPPDZ256rmi: case X86::VCMPPDZ256rri:
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case X86::VCMPPDZrmi: case X86::VCMPPDZrri:
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case X86::VCMPPSrmi: case X86::VCMPPSrri:
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case X86::VCMPPSYrmi: case X86::VCMPPSYrri:
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case X86::VCMPPSZ128rmi: case X86::VCMPPSZ128rri:
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case X86::VCMPPSZ256rmi: case X86::VCMPPSZ256rri:
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case X86::VCMPPSZrmi: case X86::VCMPPSZrri:
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case X86::VCMPSDrm: case X86::VCMPSDrr:
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case X86::VCMPSDZrm: case X86::VCMPSDZrr:
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case X86::VCMPSDrm_Int: case X86::VCMPSDrr_Int:
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case X86::VCMPSDZrm_Int: case X86::VCMPSDZrr_Int:
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case X86::VCMPSSrm: case X86::VCMPSSrr:
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case X86::VCMPSSZrm: case X86::VCMPSSZrr:
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case X86::VCMPSSrm_Int: case X86::VCMPSSrr_Int:
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case X86::VCMPSSZrm_Int: case X86::VCMPSSZrr_Int:
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case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik:
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case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik:
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case X86::VCMPPDZrmik: case X86::VCMPPDZrrik:
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case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik:
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case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik:
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case X86::VCMPPSZrmik: case X86::VCMPPSZrrik:
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case X86::VCMPSDZrm_Intk: case X86::VCMPSDZrr_Intk:
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case X86::VCMPSSZrm_Intk: case X86::VCMPSSZrr_Intk:
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case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik:
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case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik:
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case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik:
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case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik:
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case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik:
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case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik:
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case X86::VCMPPDZrrib: case X86::VCMPPDZrribk:
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case X86::VCMPPSZrrib: case X86::VCMPPSZrribk:
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case X86::VCMPSDZrrb_Int: case X86::VCMPSDZrrb_Intk:
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case X86::VCMPSSZrrb_Int: case X86::VCMPSSZrrb_Intk:
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if (Imm >= 0 && Imm <= 31) {
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OS << '\t';
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printCMPMnemonic(MI, /*IsVCMP*/true, OS);
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unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2;
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if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
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if (Desc.TSFlags & X86II::EVEX_B) {
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// Broadcast form.
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// Load size is based on W-bit.
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if (Desc.TSFlags & X86II::VEX_W)
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printqwordmem(MI, CurOp--, OS);
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else
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printdwordmem(MI, CurOp--, OS);
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// Print the number of elements broadcasted.
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unsigned NumElts;
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if (Desc.TSFlags & X86II::EVEX_L2)
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NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16;
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else if (Desc.TSFlags & X86II::VEX_L)
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NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8;
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else
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NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4;
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OS << "{1to" << NumElts << "}";
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} else {
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if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
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printdwordmem(MI, CurOp--, OS);
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else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
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printqwordmem(MI, CurOp--, OS);
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else if (Desc.TSFlags & X86II::EVEX_L2)
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printzmmwordmem(MI, CurOp--, OS);
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else if (Desc.TSFlags & X86II::VEX_L)
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printymmwordmem(MI, CurOp--, OS);
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else
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printxmmwordmem(MI, CurOp--, OS);
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}
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} else {
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if (Desc.TSFlags & X86II::EVEX_B)
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OS << "{sae}, ";
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printOperand(MI, CurOp--, OS);
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}
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OS << ", ";
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printOperand(MI, CurOp--, OS);
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OS << ", ";
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printOperand(MI, 0, OS);
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if (CurOp > 0) {
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// Print mask operand.
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OS << " {";
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printOperand(MI, CurOp--, OS);
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OS << "}";
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}
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return true;
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}
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break;
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case X86::VPCOMBmi: case X86::VPCOMBri:
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case X86::VPCOMDmi: case X86::VPCOMDri:
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case X86::VPCOMQmi: case X86::VPCOMQri:
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case X86::VPCOMUBmi: case X86::VPCOMUBri:
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case X86::VPCOMUDmi: case X86::VPCOMUDri:
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case X86::VPCOMUQmi: case X86::VPCOMUQri:
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case X86::VPCOMUWmi: case X86::VPCOMUWri:
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case X86::VPCOMWmi: case X86::VPCOMWri:
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if (Imm >= 0 && Imm <= 7) {
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OS << '\t';
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printVPCOMMnemonic(MI, OS);
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if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem)
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printxmmwordmem(MI, 2, OS);
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else
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printOperand(MI, 2, OS);
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OS << ", ";
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printOperand(MI, 1, OS);
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OS << ", ";
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printOperand(MI, 0, OS);
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return true;
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}
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break;
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case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri:
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case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri:
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case X86::VPCMPBZrmi: case X86::VPCMPBZrri:
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case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rri:
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case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rri:
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case X86::VPCMPDZrmi: case X86::VPCMPDZrri:
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case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rri:
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case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rri:
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case X86::VPCMPQZrmi: case X86::VPCMPQZrri:
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case X86::VPCMPUBZ128rmi: case X86::VPCMPUBZ128rri:
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case X86::VPCMPUBZ256rmi: case X86::VPCMPUBZ256rri:
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case X86::VPCMPUBZrmi: case X86::VPCMPUBZrri:
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case X86::VPCMPUDZ128rmi: case X86::VPCMPUDZ128rri:
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case X86::VPCMPUDZ256rmi: case X86::VPCMPUDZ256rri:
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case X86::VPCMPUDZrmi: case X86::VPCMPUDZrri:
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case X86::VPCMPUQZ128rmi: case X86::VPCMPUQZ128rri:
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case X86::VPCMPUQZ256rmi: case X86::VPCMPUQZ256rri:
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case X86::VPCMPUQZrmi: case X86::VPCMPUQZrri:
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case X86::VPCMPUWZ128rmi: case X86::VPCMPUWZ128rri:
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case X86::VPCMPUWZ256rmi: case X86::VPCMPUWZ256rri:
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case X86::VPCMPUWZrmi: case X86::VPCMPUWZrri:
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case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rri:
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case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rri:
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case X86::VPCMPWZrmi: case X86::VPCMPWZrri:
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case X86::VPCMPBZ128rmik: case X86::VPCMPBZ128rrik:
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case X86::VPCMPBZ256rmik: case X86::VPCMPBZ256rrik:
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case X86::VPCMPBZrmik: case X86::VPCMPBZrrik:
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case X86::VPCMPDZ128rmik: case X86::VPCMPDZ128rrik:
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case X86::VPCMPDZ256rmik: case X86::VPCMPDZ256rrik:
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case X86::VPCMPDZrmik: case X86::VPCMPDZrrik:
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case X86::VPCMPQZ128rmik: case X86::VPCMPQZ128rrik:
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case X86::VPCMPQZ256rmik: case X86::VPCMPQZ256rrik:
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case X86::VPCMPQZrmik: case X86::VPCMPQZrrik:
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case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik:
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case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik:
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case X86::VPCMPUBZrmik: case X86::VPCMPUBZrrik:
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case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik:
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case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik:
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case X86::VPCMPUDZrmik: case X86::VPCMPUDZrrik:
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case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik:
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case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik:
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case X86::VPCMPUQZrmik: case X86::VPCMPUQZrrik:
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case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik:
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case X86::VPCMPUWZ256rmik: case X86::VPCMPUWZ256rrik:
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case X86::VPCMPUWZrmik: case X86::VPCMPUWZrrik:
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case X86::VPCMPWZ128rmik: case X86::VPCMPWZ128rrik:
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case X86::VPCMPWZ256rmik: case X86::VPCMPWZ256rrik:
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case X86::VPCMPWZrmik: case X86::VPCMPWZrrik:
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case X86::VPCMPDZ128rmib: case X86::VPCMPDZ128rmibk:
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case X86::VPCMPDZ256rmib: case X86::VPCMPDZ256rmibk:
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case X86::VPCMPDZrmib: case X86::VPCMPDZrmibk:
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case X86::VPCMPQZ128rmib: case X86::VPCMPQZ128rmibk:
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case X86::VPCMPQZ256rmib: case X86::VPCMPQZ256rmibk:
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case X86::VPCMPQZrmib: case X86::VPCMPQZrmibk:
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case X86::VPCMPUDZ128rmib: case X86::VPCMPUDZ128rmibk:
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case X86::VPCMPUDZ256rmib: case X86::VPCMPUDZ256rmibk:
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case X86::VPCMPUDZrmib: case X86::VPCMPUDZrmibk:
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case X86::VPCMPUQZ128rmib: case X86::VPCMPUQZ128rmibk:
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case X86::VPCMPUQZ256rmib: case X86::VPCMPUQZ256rmibk:
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case X86::VPCMPUQZrmib: case X86::VPCMPUQZrmibk:
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if ((Imm >= 0 && Imm <= 2) || (Imm >= 4 && Imm <= 6)) {
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OS << '\t';
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printVPCMPMnemonic(MI, OS);
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unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2;
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if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
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if (Desc.TSFlags & X86II::EVEX_B) {
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// Broadcast form.
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// Load size is based on W-bit as only D and Q are supported.
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if (Desc.TSFlags & X86II::VEX_W)
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printqwordmem(MI, CurOp--, OS);
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else
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printdwordmem(MI, CurOp--, OS);
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// Print the number of elements broadcasted.
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unsigned NumElts;
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if (Desc.TSFlags & X86II::EVEX_L2)
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NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16;
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else if (Desc.TSFlags & X86II::VEX_L)
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NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8;
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else
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NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4;
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OS << "{1to" << NumElts << "}";
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} else {
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if (Desc.TSFlags & X86II::EVEX_L2)
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printzmmwordmem(MI, CurOp--, OS);
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else if (Desc.TSFlags & X86II::VEX_L)
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printymmwordmem(MI, CurOp--, OS);
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else
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printxmmwordmem(MI, CurOp--, OS);
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}
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} else {
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printOperand(MI, CurOp--, OS);
|
|
}
|
|
|
|
OS << ", ";
|
|
printOperand(MI, CurOp--, OS);
|
|
OS << ", ";
|
|
printOperand(MI, 0, OS);
|
|
if (CurOp > 0) {
|
|
// Print mask operand.
|
|
OS << " {";
|
|
printOperand(MI, CurOp--, OS);
|
|
OS << "}";
|
|
}
|
|
|
|
return true;
|
|
}
|
|
break;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
|
|
raw_ostream &O) {
|
|
const MCOperand &Op = MI->getOperand(OpNo);
|
|
if (Op.isReg()) {
|
|
printRegName(O, Op.getReg());
|
|
} else if (Op.isImm()) {
|
|
// Print immediates as signed values.
|
|
int64_t Imm = Op.getImm();
|
|
O << markup("<imm:") << '$' << formatImm(Imm) << markup(">");
|
|
|
|
// TODO: This should be in a helper function in the base class, so it can
|
|
// be used by other printers.
|
|
|
|
// If there are no instruction-specific comments, add a comment clarifying
|
|
// the hex value of the immediate operand when it isn't in the range
|
|
// [-256,255].
|
|
if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256)) {
|
|
// Don't print unnecessary hex sign bits.
|
|
if (Imm == (int16_t)(Imm))
|
|
*CommentStream << format("imm = 0x%" PRIX16 "\n", (uint16_t)Imm);
|
|
else if (Imm == (int32_t)(Imm))
|
|
*CommentStream << format("imm = 0x%" PRIX32 "\n", (uint32_t)Imm);
|
|
else
|
|
*CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Imm);
|
|
}
|
|
} else {
|
|
assert(Op.isExpr() && "unknown operand kind in printOperand");
|
|
O << markup("<imm:") << '$';
|
|
Op.getExpr()->print(O, &MAI);
|
|
O << markup(">");
|
|
}
|
|
}
|
|
|
|
void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
// Do not print the exact form of the memory operand if it references a known
|
|
// binary object.
|
|
if (SymbolizeOperands && MIA) {
|
|
uint64_t Target;
|
|
if (MIA->evaluateBranch(*MI, 0, 0, Target))
|
|
return;
|
|
if (MIA->evaluateMemoryOperandAddress(*MI, 0, 0))
|
|
return;
|
|
}
|
|
|
|
const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
|
|
const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
|
|
const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp);
|
|
|
|
O << markup("<mem:");
|
|
|
|
// If this has a segment register, print it.
|
|
printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
|
|
|
|
if (DispSpec.isImm()) {
|
|
int64_t DispVal = DispSpec.getImm();
|
|
if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
|
|
O << formatImm(DispVal);
|
|
} else {
|
|
assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
|
|
DispSpec.getExpr()->print(O, &MAI);
|
|
}
|
|
|
|
if (IndexReg.getReg() || BaseReg.getReg()) {
|
|
O << '(';
|
|
if (BaseReg.getReg())
|
|
printOperand(MI, Op + X86::AddrBaseReg, O);
|
|
|
|
if (IndexReg.getReg()) {
|
|
O << ',';
|
|
printOperand(MI, Op + X86::AddrIndexReg, O);
|
|
unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm();
|
|
if (ScaleVal != 1) {
|
|
O << ',' << markup("<imm:") << ScaleVal // never printed in hex.
|
|
<< markup(">");
|
|
}
|
|
}
|
|
O << ')';
|
|
}
|
|
|
|
O << markup(">");
|
|
}
|
|
|
|
void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
O << markup("<mem:");
|
|
|
|
// If this has a segment register, print it.
|
|
printOptionalSegReg(MI, Op + 1, O);
|
|
|
|
O << "(";
|
|
printOperand(MI, Op, O);
|
|
O << ")";
|
|
|
|
O << markup(">");
|
|
}
|
|
|
|
void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
O << markup("<mem:");
|
|
|
|
O << "%es:(";
|
|
printOperand(MI, Op, O);
|
|
O << ")";
|
|
|
|
O << markup(">");
|
|
}
|
|
|
|
void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
const MCOperand &DispSpec = MI->getOperand(Op);
|
|
|
|
O << markup("<mem:");
|
|
|
|
// If this has a segment register, print it.
|
|
printOptionalSegReg(MI, Op + 1, O);
|
|
|
|
if (DispSpec.isImm()) {
|
|
O << formatImm(DispSpec.getImm());
|
|
} else {
|
|
assert(DispSpec.isExpr() && "non-immediate displacement?");
|
|
DispSpec.getExpr()->print(O, &MAI);
|
|
}
|
|
|
|
O << markup(">");
|
|
}
|
|
|
|
void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
|
|
raw_ostream &O) {
|
|
if (MI->getOperand(Op).isExpr())
|
|
return printOperand(MI, Op, O);
|
|
|
|
O << markup("<imm:") << '$' << formatImm(MI->getOperand(Op).getImm() & 0xff)
|
|
<< markup(">");
|
|
}
|
|
|
|
void X86ATTInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
|
|
raw_ostream &OS) {
|
|
const MCOperand &Op = MI->getOperand(OpNo);
|
|
unsigned Reg = Op.getReg();
|
|
// Override the default printing to print st(0) instead st.
|
|
if (Reg == X86::ST0)
|
|
OS << markup("<reg:") << "%st(0)" << markup(">");
|
|
else
|
|
printRegName(OS, Reg);
|
|
}
|