ba228181c2
Linking large Hexagon binaries (e.g. ASan runtime with >8 MiB of text) fails with R_HEX_B22_PCREL / R_HEX_PLT_B22_PCREL relocation overflow on calls to PLT entries, even though the thunk infrastructure exists and needsThunks is set. needsThunk() always used s.getVA() to compute the branch destination, even for PLT calls where the actual destination is the PLT entry. This meant the distance check used the wrong address and failed to create thunks when the PLT entry was out of B22_PCREL range. Fix by using s.getPltVA() when expr == R_PLT_PC. Also override getThunkSectionSpacing() so ThunkSections are pre-created at appropriate intervals for large binaries.
723 lines
22 KiB
C++
723 lines
22 KiB
C++
//===-- Hexagon.cpp -------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "InputFiles.h"
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#include "OutputSections.h"
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#include "RelocScan.h"
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#include "SymbolTable.h"
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#include "Symbols.h"
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#include "SyntheticSections.h"
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#include "Target.h"
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#include "Thunks.h"
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#include "lld/Common/ErrorHandler.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/Support/ELFAttributes.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/HexagonAttributeParser.h"
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#include "llvm/Support/HexagonAttributes.h"
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#include "llvm/Support/LEB128.h"
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using namespace llvm;
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using namespace llvm::object;
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using namespace llvm::support::endian;
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using namespace llvm::ELF;
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using namespace lld;
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using namespace lld::elf;
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namespace {
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class Hexagon final : public TargetInfo {
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public:
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Hexagon(Ctx &);
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uint32_t calcEFlags() const override;
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RelExpr getRelExpr(RelType type, const Symbol &s,
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const uint8_t *loc) const override;
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RelType getDynRel(RelType type) const override;
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int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
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template <class ELFT, class RelTy>
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void scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels);
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void scanSection(InputSectionBase &sec) override {
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elf::scanSection1<Hexagon, ELF32LE>(*this, sec);
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}
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void finalizeRelocScan() override;
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bool needsThunk(RelExpr expr, RelType type, const InputFile *file,
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uint64_t branchAddr, const Symbol &s,
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int64_t a) const override;
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uint32_t getThunkSectionSpacing() const override;
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bool inBranchRange(RelType type, uint64_t src, uint64_t dst) const override;
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void relocate(uint8_t *loc, const Relocation &rel,
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uint64_t val) const override;
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void writePltHeader(uint8_t *buf) const override;
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void writePlt(uint8_t *buf, const Symbol &sym,
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uint64_t pltEntryAddr) const override;
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};
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} // namespace
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Hexagon::Hexagon(Ctx &ctx) : TargetInfo(ctx) {
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pltRel = R_HEX_JMP_SLOT;
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relativeRel = R_HEX_RELATIVE;
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gotRel = R_HEX_GLOB_DAT;
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symbolicRel = R_HEX_32;
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gotBaseSymInGotPlt = true;
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// The zero'th GOT entry is reserved for the address of _DYNAMIC. The
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// next 3 are reserved for the dynamic loader.
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gotPltHeaderEntriesNum = 4;
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pltEntrySize = 16;
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pltHeaderSize = 32;
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// Hexagon Linux uses 64K pages by default.
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defaultMaxPageSize = 0x10000;
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tlsGotRel = R_HEX_TPREL_32;
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tlsModuleIndexRel = R_HEX_DTPMOD_32;
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tlsOffsetRel = R_HEX_DTPREL_32;
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needsThunks = true;
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}
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uint32_t Hexagon::calcEFlags() const {
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// The architecture revision must always be equal to or greater than
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// greatest revision in the list of inputs.
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std::optional<uint32_t> ret;
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for (InputFile *f : ctx.objectFiles) {
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uint32_t eflags = cast<ObjFile<ELF32LE>>(f)->getObj().getHeader().e_flags;
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if (!ret || eflags > *ret)
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ret = eflags;
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}
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return ret.value_or(/* Default Arch Rev: */ EF_HEXAGON_MACH_V68);
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}
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static uint32_t applyMask(uint32_t mask, uint32_t data) {
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uint32_t result = 0;
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size_t off = 0;
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for (size_t bit = 0; bit != 32; ++bit) {
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uint32_t valBit = (data >> off) & 1;
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uint32_t maskBit = (mask >> bit) & 1;
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if (maskBit) {
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result |= (valBit << bit);
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++off;
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}
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}
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return result;
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}
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// Only needed to support relocations used by relocateNonAlloc and
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// preprocessRelocs.
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RelExpr Hexagon::getRelExpr(RelType type, const Symbol &s,
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const uint8_t *loc) const {
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switch (type) {
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case R_HEX_NONE:
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return R_NONE;
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case R_HEX_32:
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return R_ABS;
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case R_HEX_32_PCREL:
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return R_PC;
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default:
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Err(ctx) << getErrorLoc(ctx, loc) << "unknown relocation (" << type.v
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<< ") against symbol " << &s;
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return R_NONE;
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}
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}
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template <class ELFT, class RelTy>
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void Hexagon::scanSectionImpl(InputSectionBase &sec, Relocs<RelTy> rels) {
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RelocScan rs(ctx, &sec);
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sec.relocations.reserve(rels.size());
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for (auto it = rels.begin(); it != rels.end(); ++it) {
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const RelTy &rel = *it;
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uint32_t symIdx = rel.getSymbol(false);
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Symbol &sym = sec.getFile<ELFT>()->getSymbol(symIdx);
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uint64_t offset = rel.r_offset;
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RelType type = rel.getType(false);
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if (sym.isUndefined() && symIdx != 0 &&
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rs.maybeReportUndefined(cast<Undefined>(sym), offset))
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continue;
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int64_t addend = rs.getAddend<ELFT>(rel, type);
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RelExpr expr;
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// Relocation types that only need a RelExpr set `expr` and break out of
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// the switch to reach rs.process(). Types that need special handling
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// (fast-path helpers, TLS) call a handler and use `continue`.
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switch (type) {
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case R_HEX_NONE:
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continue;
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// Absolute relocations:
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case R_HEX_6_X:
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case R_HEX_8_X:
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case R_HEX_9_X:
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case R_HEX_10_X:
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case R_HEX_11_X:
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case R_HEX_12_X:
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case R_HEX_16_X:
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case R_HEX_32:
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case R_HEX_32_6_X:
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case R_HEX_HI16:
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case R_HEX_LO16:
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case R_HEX_DTPREL_32:
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expr = R_ABS;
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break;
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// PC-relative relocations:
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case R_HEX_B9_PCREL:
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case R_HEX_B13_PCREL:
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case R_HEX_B15_PCREL:
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case R_HEX_6_PCREL_X:
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case R_HEX_32_PCREL:
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rs.processR_PC(type, offset, addend, sym);
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continue;
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// PLT-generating relocations:
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case R_HEX_B9_PCREL_X:
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case R_HEX_B15_PCREL_X:
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case R_HEX_B22_PCREL:
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case R_HEX_PLT_B22_PCREL:
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case R_HEX_B22_PCREL_X:
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case R_HEX_B32_PCREL_X:
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rs.processR_PLT_PC(type, offset, addend, sym);
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continue;
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case R_HEX_GD_PLT_B22_PCREL:
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case R_HEX_GD_PLT_B22_PCREL_X:
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case R_HEX_GD_PLT_B32_PCREL_X:
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// GD PLT: call foo@GDPLT becomes call __tls_get_addr.
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// Record R_PLT_PC on the TLS symbol; finalizeRelocScan (called
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// single-threaded after scanning) will create __tls_get_addr and
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// rebind these relocations. We cannot access the symbol table here
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// because scanSectionImpl runs in parallel.
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sec.addReloc({R_PLT_PC, type, offset, addend, &sym});
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continue;
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// GOT-generating relocations:
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case R_HEX_GOT_11_X:
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case R_HEX_GOT_16_X:
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case R_HEX_GOT_32_6_X:
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ctx.in.gotPlt->hasGotPltOffRel.store(true, std::memory_order_relaxed);
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expr = R_GOTPLT;
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break;
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// GOTREL relocations:
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case R_HEX_GOTREL_11_X:
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case R_HEX_GOTREL_16_X:
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case R_HEX_GOTREL_32_6_X:
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case R_HEX_GOTREL_HI16:
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case R_HEX_GOTREL_LO16:
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ctx.in.gotPlt->hasGotPltOffRel.store(true, std::memory_order_relaxed);
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expr = R_GOTPLTREL;
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break;
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// TLS relocations:
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case R_HEX_TPREL_11_X:
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case R_HEX_TPREL_16:
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case R_HEX_TPREL_16_X:
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case R_HEX_TPREL_32_6_X:
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case R_HEX_TPREL_HI16:
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case R_HEX_TPREL_LO16:
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if (rs.checkTlsLe(offset, sym, type))
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continue;
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expr = R_TPREL;
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break;
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case R_HEX_IE_32_6_X:
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case R_HEX_IE_16_X:
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case R_HEX_IE_HI16:
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case R_HEX_IE_LO16:
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// There is no IE to LE optimization.
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rs.handleTlsIe<false>(R_GOT, type, offset, addend, sym);
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continue;
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case R_HEX_IE_GOT_11_X:
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case R_HEX_IE_GOT_16_X:
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case R_HEX_IE_GOT_32_6_X:
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case R_HEX_IE_GOT_HI16:
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case R_HEX_IE_GOT_LO16:
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ctx.in.gotPlt->hasGotPltOffRel.store(true, std::memory_order_relaxed);
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rs.handleTlsIe<false>(R_GOTPLT, type, offset, addend, sym);
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continue;
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case R_HEX_GD_GOT_11_X:
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case R_HEX_GD_GOT_16_X:
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case R_HEX_GD_GOT_32_6_X:
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sym.setFlags(NEEDS_TLSGD);
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ctx.in.gotPlt->hasGotPltOffRel.store(true, std::memory_order_relaxed);
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sec.addReloc({R_TLSGD_GOTPLT, type, offset, addend, &sym});
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continue;
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default:
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Err(ctx) << getErrorLoc(ctx, sec.content().data() + offset)
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<< "unknown relocation (" << type.v << ") against symbol "
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<< &sym;
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continue;
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}
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rs.process(expr, type, offset, sym, addend);
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}
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}
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// There are (arguably too) many relocation masks for the DSP's
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// R_HEX_6_X type. The table below is used to select the correct mask
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// for the given instruction.
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struct InstructionMask {
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uint32_t cmpMask;
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uint32_t relocMask;
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};
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static const InstructionMask r6[] = {
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{0x38000000, 0x0000201f}, {0x39000000, 0x0000201f},
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{0x3e000000, 0x00001f80}, {0x3f000000, 0x00001f80},
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{0x40000000, 0x000020f8}, {0x41000000, 0x000007e0},
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{0x42000000, 0x000020f8}, {0x43000000, 0x000007e0},
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{0x44000000, 0x000020f8}, {0x45000000, 0x000007e0},
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{0x46000000, 0x000020f8}, {0x47000000, 0x000007e0},
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{0x6a000000, 0x00001f80}, {0x7c000000, 0x001f2000},
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{0x9a000000, 0x00000f60}, {0x9b000000, 0x00000f60},
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{0x9c000000, 0x00000f60}, {0x9d000000, 0x00000f60},
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{0x9f000000, 0x001f0100}, {0xab000000, 0x0000003f},
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{0xad000000, 0x0000003f}, {0xaf000000, 0x00030078},
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{0xd7000000, 0x006020e0}, {0xd8000000, 0x006020e0},
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{0xdb000000, 0x006020e0}, {0xdf000000, 0x006020e0}};
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constexpr uint32_t instParsePacketEnd = 0x0000c000;
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static bool isDuplex(uint32_t insn) {
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// Duplex forms have a fixed mask and parse bits 15:14 are always
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// zero. Non-duplex insns will always have at least one bit set in the
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// parse field.
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return (instParsePacketEnd & insn) == 0;
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}
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static uint32_t findMaskR6(Ctx &ctx, uint32_t insn) {
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if (isDuplex(insn))
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return 0x03f00000;
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for (InstructionMask i : r6)
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if ((0xff000000 & insn) == i.cmpMask)
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return i.relocMask;
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Err(ctx) << "unrecognized instruction for 6_X relocation: 0x"
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<< utohexstr(insn, true);
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return 0;
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}
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static uint32_t findMaskR8(uint32_t insn) {
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if (isDuplex(insn))
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return 0x03f00000;
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if ((0xff000000 & insn) == 0xde000000)
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return 0x00e020e8;
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if ((0xff000000 & insn) == 0x3c000000)
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return 0x0000207f;
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return 0x00001fe0;
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}
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static uint32_t findMaskR11(uint32_t insn) {
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if (isDuplex(insn))
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return 0x03f00000;
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if ((0xff000000 & insn) == 0xa1000000)
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return 0x060020ff;
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return 0x06003fe0;
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}
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static uint32_t findMaskR16(Ctx &ctx, uint32_t insn) {
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if (isDuplex(insn))
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return 0x03f00000;
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// Clear the end-packet-parse bits:
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insn = insn & ~instParsePacketEnd;
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if ((0xff000000 & insn) == 0x48000000)
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return 0x061f20ff;
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if ((0xff000000 & insn) == 0x49000000)
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return 0x061f3fe0;
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if ((0xff000000 & insn) == 0x78000000)
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return 0x00df3fe0;
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if ((0xff000000 & insn) == 0xb0000000)
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return 0x0fe03fe0;
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if ((0xff802000 & insn) == 0x74000000)
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return 0x00001fe0;
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if ((0xff802000 & insn) == 0x74002000)
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return 0x00001fe0;
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if ((0xff802000 & insn) == 0x74800000)
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return 0x00001fe0;
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if ((0xff802000 & insn) == 0x74802000)
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return 0x00001fe0;
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for (InstructionMask i : r6)
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if ((0xff000000 & insn) == i.cmpMask)
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return i.relocMask;
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Err(ctx) << "unrecognized instruction for 16_X type: 0x" << utohexstr(insn);
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return 0;
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}
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static void or32le(uint8_t *p, int32_t v) { write32le(p, read32le(p) | v); }
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bool Hexagon::inBranchRange(RelType type, uint64_t src, uint64_t dst) const {
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int64_t offset = dst - src;
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switch (type) {
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case llvm::ELF::R_HEX_B22_PCREL:
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case llvm::ELF::R_HEX_PLT_B22_PCREL:
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case llvm::ELF::R_HEX_GD_PLT_B22_PCREL:
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case llvm::ELF::R_HEX_LD_PLT_B22_PCREL:
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return llvm::isInt<22>(offset >> 2);
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case llvm::ELF::R_HEX_B15_PCREL:
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return llvm::isInt<15>(offset >> 2);
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break;
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case llvm::ELF::R_HEX_B13_PCREL:
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return llvm::isInt<13>(offset >> 2);
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break;
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case llvm::ELF::R_HEX_B9_PCREL:
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return llvm::isInt<9>(offset >> 2);
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default:
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return true;
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}
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llvm_unreachable("unsupported relocation");
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}
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bool Hexagon::needsThunk(RelExpr expr, RelType type, const InputFile *file,
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uint64_t branchAddr, const Symbol &s,
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int64_t a) const {
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// Undefined weak symbols without PLT entries resolve to address zero.
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// Thunks are not needed since the branch target is fixed.
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if (s.isUndefined() && !s.isInPlt(ctx))
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return false;
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switch (type) {
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case R_HEX_B22_PCREL:
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case R_HEX_PLT_B22_PCREL:
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case R_HEX_GD_PLT_B22_PCREL:
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case R_HEX_LD_PLT_B22_PCREL:
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case R_HEX_B15_PCREL:
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case R_HEX_B13_PCREL:
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case R_HEX_B9_PCREL: {
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uint64_t dst = expr == R_PLT_PC ? s.getPltVA(ctx) : s.getVA(ctx, a);
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return !ctx.target->inBranchRange(type, branchAddr, dst);
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}
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default:
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return false;
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}
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}
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uint32_t Hexagon::getThunkSectionSpacing() const {
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// B22_PCREL has a range of +/- 8 MiB (22-bit signed offset * 4).
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// Pre-create ThunkSections at intervals below this to leave room for
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// thunk growth.
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return 0x800000 - 0x30000;
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}
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void Hexagon::relocate(uint8_t *loc, const Relocation &rel,
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uint64_t val) const {
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switch (rel.type) {
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case R_HEX_NONE:
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break;
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case R_HEX_6_PCREL_X:
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case R_HEX_6_X:
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or32le(loc, applyMask(findMaskR6(ctx, read32le(loc)), val));
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break;
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case R_HEX_8_X:
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or32le(loc, applyMask(findMaskR8(read32le(loc)), val));
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break;
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case R_HEX_9_X:
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or32le(loc, applyMask(0x00003fe0, val & 0x3f));
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break;
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case R_HEX_10_X:
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or32le(loc, applyMask(0x00203fe0, val & 0x3f));
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break;
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case R_HEX_11_X:
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case R_HEX_GD_GOT_11_X:
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case R_HEX_IE_GOT_11_X:
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case R_HEX_GOT_11_X:
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case R_HEX_GOTREL_11_X:
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case R_HEX_TPREL_11_X:
|
|
or32le(loc, applyMask(findMaskR11(read32le(loc)), val & 0x3f));
|
|
break;
|
|
case R_HEX_12_X:
|
|
or32le(loc, applyMask(0x000007e0, val));
|
|
break;
|
|
case R_HEX_16_X: // These relocs only have 6 effective bits.
|
|
case R_HEX_IE_16_X:
|
|
case R_HEX_IE_GOT_16_X:
|
|
case R_HEX_GD_GOT_16_X:
|
|
case R_HEX_GOT_16_X:
|
|
case R_HEX_GOTREL_16_X:
|
|
case R_HEX_TPREL_16_X:
|
|
or32le(loc, applyMask(findMaskR16(ctx, read32le(loc)), val & 0x3f));
|
|
break;
|
|
case R_HEX_TPREL_16:
|
|
or32le(loc, applyMask(findMaskR16(ctx, read32le(loc)), val & 0xffff));
|
|
break;
|
|
case R_HEX_32:
|
|
case R_HEX_32_PCREL:
|
|
case R_HEX_DTPREL_32:
|
|
or32le(loc, val);
|
|
break;
|
|
case R_HEX_32_6_X:
|
|
case R_HEX_GD_GOT_32_6_X:
|
|
case R_HEX_GOT_32_6_X:
|
|
case R_HEX_GOTREL_32_6_X:
|
|
case R_HEX_IE_GOT_32_6_X:
|
|
case R_HEX_IE_32_6_X:
|
|
case R_HEX_TPREL_32_6_X:
|
|
or32le(loc, applyMask(0x0fff3fff, val >> 6));
|
|
break;
|
|
case R_HEX_B9_PCREL:
|
|
checkInt(ctx, loc, val, 11, rel);
|
|
or32le(loc, applyMask(0x003000fe, val >> 2));
|
|
break;
|
|
case R_HEX_B9_PCREL_X:
|
|
or32le(loc, applyMask(0x003000fe, val & 0x3f));
|
|
break;
|
|
case R_HEX_B13_PCREL:
|
|
checkInt(ctx, loc, val, 15, rel);
|
|
or32le(loc, applyMask(0x00202ffe, val >> 2));
|
|
break;
|
|
case R_HEX_B15_PCREL:
|
|
checkInt(ctx, loc, val, 17, rel);
|
|
or32le(loc, applyMask(0x00df20fe, val >> 2));
|
|
break;
|
|
case R_HEX_B15_PCREL_X:
|
|
or32le(loc, applyMask(0x00df20fe, val & 0x3f));
|
|
break;
|
|
case R_HEX_B22_PCREL:
|
|
case R_HEX_GD_PLT_B22_PCREL:
|
|
case R_HEX_PLT_B22_PCREL:
|
|
checkInt(ctx, loc, val, 24, rel);
|
|
or32le(loc, applyMask(0x1ff3ffe, val >> 2));
|
|
break;
|
|
case R_HEX_B22_PCREL_X:
|
|
case R_HEX_GD_PLT_B22_PCREL_X:
|
|
or32le(loc, applyMask(0x1ff3ffe, val & 0x3f));
|
|
break;
|
|
case R_HEX_B32_PCREL_X:
|
|
case R_HEX_GD_PLT_B32_PCREL_X:
|
|
or32le(loc, applyMask(0x0fff3fff, val >> 6));
|
|
break;
|
|
case R_HEX_GOTREL_HI16:
|
|
case R_HEX_HI16:
|
|
case R_HEX_IE_GOT_HI16:
|
|
case R_HEX_IE_HI16:
|
|
case R_HEX_TPREL_HI16:
|
|
or32le(loc, applyMask(0x00c03fff, val >> 16));
|
|
break;
|
|
case R_HEX_GOTREL_LO16:
|
|
case R_HEX_LO16:
|
|
case R_HEX_IE_GOT_LO16:
|
|
case R_HEX_IE_LO16:
|
|
case R_HEX_TPREL_LO16:
|
|
or32le(loc, applyMask(0x00c03fff, val));
|
|
break;
|
|
default:
|
|
llvm_unreachable("unknown relocation");
|
|
}
|
|
}
|
|
|
|
void Hexagon::writePltHeader(uint8_t *buf) const {
|
|
const uint8_t pltData[] = {
|
|
0x00, 0x40, 0x00, 0x00, // { immext (#0)
|
|
0x1c, 0xc0, 0x49, 0x6a, // r28 = add (pc, ##GOT0@PCREL) } # @GOT0
|
|
0x0e, 0x42, 0x9c, 0xe2, // { r14 -= add (r28, #16) # offset of GOTn
|
|
0x4f, 0x40, 0x9c, 0x91, // r15 = memw (r28 + #8) # object ID at GOT2
|
|
0x3c, 0xc0, 0x9c, 0x91, // r28 = memw (r28 + #4) }# dynamic link at GOT1
|
|
0x0e, 0x42, 0x0e, 0x8c, // { r14 = asr (r14, #2) # index of PLTn
|
|
0x00, 0xc0, 0x9c, 0x52, // jumpr r28 } # call dynamic linker
|
|
0x0c, 0xdb, 0x00, 0x54, // trap0(#0xdb) # bring plt0 into 16byte alignment
|
|
};
|
|
memcpy(buf, pltData, sizeof(pltData));
|
|
|
|
// Offset from PLT0 to the GOT.
|
|
uint64_t off = ctx.in.gotPlt->getVA() - ctx.in.plt->getVA();
|
|
relocateNoSym(buf, R_HEX_B32_PCREL_X, off);
|
|
relocateNoSym(buf + 4, R_HEX_6_PCREL_X, off);
|
|
}
|
|
|
|
void Hexagon::writePlt(uint8_t *buf, const Symbol &sym,
|
|
uint64_t pltEntryAddr) const {
|
|
const uint8_t inst[] = {
|
|
0x00, 0x40, 0x00, 0x00, // { immext (#0)
|
|
0x0e, 0xc0, 0x49, 0x6a, // r14 = add (pc, ##GOTn@PCREL) }
|
|
0x1c, 0xc0, 0x8e, 0x91, // r28 = memw (r14)
|
|
0x00, 0xc0, 0x9c, 0x52, // jumpr r28
|
|
};
|
|
memcpy(buf, inst, sizeof(inst));
|
|
|
|
uint64_t gotPltEntryAddr = sym.getGotPltVA(ctx);
|
|
relocateNoSym(buf, R_HEX_B32_PCREL_X, gotPltEntryAddr - pltEntryAddr);
|
|
relocateNoSym(buf + 4, R_HEX_6_PCREL_X, gotPltEntryAddr - pltEntryAddr);
|
|
}
|
|
|
|
RelType Hexagon::getDynRel(RelType type) const {
|
|
if (type == R_HEX_32)
|
|
return type;
|
|
return R_HEX_NONE;
|
|
}
|
|
|
|
int64_t Hexagon::getImplicitAddend(const uint8_t *buf, RelType type) const {
|
|
switch (type) {
|
|
case R_HEX_NONE:
|
|
case R_HEX_GLOB_DAT:
|
|
case R_HEX_JMP_SLOT:
|
|
return 0;
|
|
case R_HEX_32:
|
|
case R_HEX_RELATIVE:
|
|
case R_HEX_DTPMOD_32:
|
|
case R_HEX_DTPREL_32:
|
|
case R_HEX_TPREL_32:
|
|
return SignExtend64<32>(read32(ctx, buf));
|
|
default:
|
|
InternalErr(ctx, buf) << "cannot read addend for relocation " << type;
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
namespace {
|
|
class HexagonAttributesSection final : public SyntheticSection {
|
|
public:
|
|
HexagonAttributesSection(Ctx &ctx)
|
|
: SyntheticSection(ctx, ".hexagon.attributes", SHT_HEXAGON_ATTRIBUTES, 0,
|
|
1) {}
|
|
|
|
size_t getSize() const override { return size; }
|
|
void writeTo(uint8_t *buf) override;
|
|
|
|
static constexpr StringRef vendor = "hexagon";
|
|
DenseMap<unsigned, unsigned> intAttr;
|
|
size_t size = 0;
|
|
};
|
|
} // namespace
|
|
|
|
static HexagonAttributesSection *
|
|
mergeAttributesSection(Ctx &ctx,
|
|
const SmallVector<InputSectionBase *, 0> §ions) {
|
|
ctx.in.hexagonAttributes = std::make_unique<HexagonAttributesSection>(ctx);
|
|
auto &merged =
|
|
static_cast<HexagonAttributesSection &>(*ctx.in.hexagonAttributes);
|
|
|
|
// Collect all tags values from attributes section.
|
|
const auto &attributesTags = HexagonAttrs::getHexagonAttributeTags();
|
|
for (const InputSectionBase *sec : sections) {
|
|
HexagonAttributeParser parser;
|
|
if (Error e = parser.parse(sec->content(), llvm::endianness::little))
|
|
Warn(ctx) << sec << ": " << std::move(e);
|
|
for (const auto &tag : attributesTags) {
|
|
switch (HexagonAttrs::AttrType(tag.attr)) {
|
|
case HexagonAttrs::ARCH:
|
|
case HexagonAttrs::HVXARCH:
|
|
if (auto i = parser.getAttributeValue(tag.attr)) {
|
|
auto r = merged.intAttr.try_emplace(tag.attr, *i);
|
|
if (!r.second)
|
|
if (r.first->second < *i)
|
|
r.first->second = *i;
|
|
}
|
|
continue;
|
|
|
|
case HexagonAttrs::HVXIEEEFP:
|
|
case HexagonAttrs::HVXQFLOAT:
|
|
case HexagonAttrs::ZREG:
|
|
case HexagonAttrs::AUDIO:
|
|
case HexagonAttrs::CABAC:
|
|
if (auto i = parser.getAttributeValue(tag.attr)) {
|
|
auto r = merged.intAttr.try_emplace(tag.attr, *i);
|
|
if (!r.second && r.first->second != *i) {
|
|
r.first->second |= *i;
|
|
}
|
|
}
|
|
continue;
|
|
}
|
|
}
|
|
}
|
|
|
|
// The total size of headers: format-version [ <section-length> "vendor-name"
|
|
// [ <file-tag> <size>.
|
|
size_t size = 5 + merged.vendor.size() + 1 + 5;
|
|
for (auto &attr : merged.intAttr)
|
|
if (attr.second != 0)
|
|
size += getULEB128Size(attr.first) + getULEB128Size(attr.second);
|
|
merged.size = size;
|
|
return &merged;
|
|
}
|
|
|
|
void HexagonAttributesSection::writeTo(uint8_t *buf) {
|
|
const size_t size = getSize();
|
|
uint8_t *const end = buf + size;
|
|
*buf = ELFAttrs::Format_Version;
|
|
write32(ctx, buf + 1, size - 1);
|
|
buf += 5;
|
|
|
|
memcpy(buf, vendor.data(), vendor.size());
|
|
buf += vendor.size() + 1;
|
|
|
|
*buf = ELFAttrs::File;
|
|
write32(ctx, buf + 1, end - buf);
|
|
buf += 5;
|
|
|
|
for (auto &attr : intAttr) {
|
|
if (attr.second == 0)
|
|
continue;
|
|
buf += encodeULEB128(attr.first, buf);
|
|
buf += encodeULEB128(attr.second, buf);
|
|
}
|
|
}
|
|
|
|
void elf::mergeHexagonAttributesSections(Ctx &ctx) {
|
|
// Find the first input SHT_HEXAGON_ATTRIBUTES; return if not found.
|
|
size_t place =
|
|
llvm::find_if(ctx.inputSections,
|
|
[](auto *s) { return s->type == SHT_HEXAGON_ATTRIBUTES; }) -
|
|
ctx.inputSections.begin();
|
|
if (place == ctx.inputSections.size())
|
|
return;
|
|
|
|
// Extract all SHT_HEXAGON_ATTRIBUTES sections into `sections`.
|
|
SmallVector<InputSectionBase *, 0> sections;
|
|
llvm::erase_if(ctx.inputSections, [&](InputSectionBase *s) {
|
|
if (s->type != SHT_HEXAGON_ATTRIBUTES)
|
|
return false;
|
|
sections.push_back(s);
|
|
return true;
|
|
});
|
|
|
|
// Add the merged section.
|
|
ctx.inputSections.insert(ctx.inputSections.begin() + place,
|
|
mergeAttributesSection(ctx, sections));
|
|
}
|
|
|
|
static bool isGDPLT(RelType type) {
|
|
switch (type) {
|
|
case R_HEX_GD_PLT_B22_PCREL:
|
|
case R_HEX_GD_PLT_B22_PCREL_X:
|
|
case R_HEX_GD_PLT_B32_PCREL_X:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
void Hexagon::finalizeRelocScan() {
|
|
Symbol *tga = nullptr;
|
|
|
|
// Scan for R_HEX_GD_PLT_* relocations (recorded as R_PLT_PC by
|
|
// scanSectionImpl) and rebind them to __tls_get_addr.
|
|
for (ELFFileBase *f : ctx.objectFiles) {
|
|
for (InputSectionBase *s : f->getSections()) {
|
|
auto *isec = dyn_cast_or_null<InputSection>(s);
|
|
if (!isec || !isec->isLive())
|
|
continue;
|
|
for (Relocation &rel : isec->relocs()) {
|
|
if (rel.expr != R_PLT_PC || !isGDPLT(rel.type))
|
|
continue;
|
|
if (!tga) {
|
|
tga = ctx.symtab->addSymbol(Undefined{ctx.internalFile,
|
|
"__tls_get_addr", STB_GLOBAL,
|
|
STV_DEFAULT, STT_FUNC});
|
|
tga->isUsedInRegularObj = true;
|
|
tga->used = true;
|
|
tga->isPreemptible = true;
|
|
tga->setFlags(NEEDS_PLT);
|
|
}
|
|
rel.sym = tga;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void elf::setHexagonTargetInfo(Ctx &ctx) { ctx.target.reset(new Hexagon(ctx)); }
|