Kazu Hirata 8a20e2b3d3 [llvm] Use Optional::getValueOr (NFC)

2021-01-12 21:43:50 -08:00

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AsmParser

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Disassembler

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MCTargetDesc

[VE] Change default CPU name to "generic"

2021-01-04 20:09:57 +09:00

TargetInfo

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CMakeLists.txt

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LVLGen.cpp

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VE.h

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VE.td

[VE] Change default CPU name to "generic"

2021-01-04 20:09:57 +09:00

VEAsmPrinter.cpp

[VE][NFC] Update comments to match the generated instructions

2021-01-07 15:13:24 +09:00

VECallingConv.td

[VE] Correct VMP allocation in calling conv

2020-12-21 22:42:24 +09:00

VEFrameLowering.cpp

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VEFrameLowering.h

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VEInstrBuilder.h

[VE] Support SJLJ exception related instructions

2021-01-05 20:19:15 +09:00

VEInstrFormats.td

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VEInstrInfo.cpp

[VE] Support copy of vector mask registers

2020-12-19 09:16:43 +09:00

VEInstrInfo.h

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VEInstrInfo.td

[VE] Extract & insert vector element isel

2021-01-08 11:46:59 +01:00

VEInstrIntrinsicVL.gen.td

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VEInstrIntrinsicVL.td

[VE] Support additional VMRGW and VMV intrinsic instructions

2021-01-11 20:50:31 +09:00

VEInstrPatternsVec.td

[VE] Extract & insert vector element isel

2021-01-08 11:46:59 +01:00

VEInstrVec.td

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VEISelDAGToDAG.cpp

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VEISelLowering.cpp

[VP] ISD helper functions [VE] isel for vp_add, vp_and

2021-01-08 14:29:45 +01:00

VEISelLowering.h

[VE] Extract & insert vector element isel

2021-01-08 11:46:59 +01:00

VEMachineFunctionInfo.cpp

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VEMachineFunctionInfo.h

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VEMCInstLower.cpp

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VERegisterInfo.cpp

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VERegisterInfo.h

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VERegisterInfo.td

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VESubtarget.cpp

[VE] Change default CPU name to "generic"

2021-01-04 20:09:57 +09:00

VESubtarget.h

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VETargetMachine.cpp

[llvm] Use Optional::getValueOr (NFC)

2021-01-12 21:43:50 -08:00

VETargetMachine.h

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VETargetTransformInfo.h

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VVPInstrInfo.td

[VE] Vector 'and' isel and tests

2020-12-23 13:29:29 +01:00

VVPInstrPatternsVec.td

[VE] Vector 'and' isel and tests

2020-12-23 13:29:29 +01:00

VVPNodes.def

[VP] ISD helper functions [VE] isel for vp_add, vp_and

2021-01-08 14:29:45 +01:00