2c0a2261b1
Transform `select_cc t1, t2, -1, 0` for floats into a vector comparison which generates a mask, which is later on combined with potential vectorized DUPs.
379 lines
12 KiB
LLVM
379 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFULLFP16
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; RUN: llc < %s -mtriple=aarch64 --enable-no-nans-fp-math | FileCheck %s --check-prefixes=CHECK,CHECK-NONANS
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; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FULLFP16
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define <1 x float> @dup_v1i32_oeq(float %a, float %b) {
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; CHECK-LABEL: dup_v1i32_oeq:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcmeq s0, s0, s1
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp oeq float %a, %b
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%vcmpd.i = sext i1 %0 to i32
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%vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0
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%1 = bitcast <1 x i32> %vecinit.i to <1 x float>
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ret <1 x float> %1
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}
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define <1 x float> @dup_v1i32_ogt(float %a, float %b) {
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; CHECK-LABEL: dup_v1i32_ogt:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcmgt s0, s0, s1
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp ogt float %a, %b
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%vcmpd.i = sext i1 %0 to i32
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%vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0
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%1 = bitcast <1 x i32> %vecinit.i to <1 x float>
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ret <1 x float> %1
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}
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define <1 x float> @dup_v1i32_oge(float %a, float %b) {
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; CHECK-LABEL: dup_v1i32_oge:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcmge s0, s0, s1
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp oge float %a, %b
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%vcmpd.i = sext i1 %0 to i32
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%vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0
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%1 = bitcast <1 x i32> %vecinit.i to <1 x float>
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ret <1 x float> %1
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}
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define <1 x float> @dup_v1i32_olt(float %a, float %b) {
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; CHECK-LABEL: dup_v1i32_olt:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcmgt s0, s1, s0
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp olt float %a, %b
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%vcmpd.i = sext i1 %0 to i32
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%vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0
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%1 = bitcast <1 x i32> %vecinit.i to <1 x float>
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ret <1 x float> %1
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}
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define <1 x float> @dup_v1i32_ole(float %a, float %b) {
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; CHECK-LABEL: dup_v1i32_ole:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcmge s0, s1, s0
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp ole float %a, %b
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%vcmpd.i = sext i1 %0 to i32
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%vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0
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%1 = bitcast <1 x i32> %vecinit.i to <1 x float>
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ret <1 x float> %1
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}
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define <1 x float> @dup_v1i32_one(float %a, float %b) {
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; CHECK-NOFULLFP16-LABEL: dup_v1i32_one:
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; CHECK-NOFULLFP16: // %bb.0: // %entry
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; CHECK-NOFULLFP16-NEXT: fcmgt s2, s0, s1
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; CHECK-NOFULLFP16-NEXT: fcmgt s0, s1, s0
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; CHECK-NOFULLFP16-NEXT: orr v0.16b, v0.16b, v2.16b
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; CHECK-NOFULLFP16-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NOFULLFP16-NEXT: ret
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;
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; CHECK-NONANS-LABEL: dup_v1i32_one:
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; CHECK-NONANS: // %bb.0: // %entry
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; CHECK-NONANS-NEXT: fcmeq s0, s0, s1
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; CHECK-NONANS-NEXT: mvn v0.8b, v0.8b
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; CHECK-NONANS-NEXT: ret
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;
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; CHECK-FULLFP16-LABEL: dup_v1i32_one:
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; CHECK-FULLFP16: // %bb.0: // %entry
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; CHECK-FULLFP16-NEXT: fcmgt s2, s0, s1
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; CHECK-FULLFP16-NEXT: fcmgt s0, s1, s0
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; CHECK-FULLFP16-NEXT: orr v0.16b, v0.16b, v2.16b
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; CHECK-FULLFP16-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-FULLFP16-NEXT: ret
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entry:
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%0 = fcmp one float %a, %b
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%vcmpd.i = sext i1 %0 to i32
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%vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0
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%1 = bitcast <1 x i32> %vecinit.i to <1 x float>
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ret <1 x float> %1
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}
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define <1 x float> @dup_v1i32_ord(float %a, float %b) {
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; CHECK-LABEL: dup_v1i32_ord:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcmge s2, s0, s1
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; CHECK-NEXT: fcmgt s0, s1, s0
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; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp ord float %a, %b
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%vcmpd.i = sext i1 %0 to i32
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%vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0
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%1 = bitcast <1 x i32> %vecinit.i to <1 x float>
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ret <1 x float> %1
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}
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define <1 x float> @dup_v1i32_ueq(float %a, float %b) {
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; CHECK-NOFULLFP16-LABEL: dup_v1i32_ueq:
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; CHECK-NOFULLFP16: // %bb.0: // %entry
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; CHECK-NOFULLFP16-NEXT: fcmgt s2, s0, s1
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; CHECK-NOFULLFP16-NEXT: fcmgt s0, s1, s0
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; CHECK-NOFULLFP16-NEXT: orr v0.16b, v0.16b, v2.16b
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; CHECK-NOFULLFP16-NEXT: mvn v0.8b, v0.8b
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; CHECK-NOFULLFP16-NEXT: ret
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;
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; CHECK-NONANS-LABEL: dup_v1i32_ueq:
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; CHECK-NONANS: // %bb.0: // %entry
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; CHECK-NONANS-NEXT: fcmeq s0, s0, s1
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; CHECK-NONANS-NEXT: ret
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;
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; CHECK-FULLFP16-LABEL: dup_v1i32_ueq:
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; CHECK-FULLFP16: // %bb.0: // %entry
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; CHECK-FULLFP16-NEXT: fcmgt s2, s0, s1
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; CHECK-FULLFP16-NEXT: fcmgt s0, s1, s0
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; CHECK-FULLFP16-NEXT: orr v0.16b, v0.16b, v2.16b
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; CHECK-FULLFP16-NEXT: mvn v0.8b, v0.8b
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; CHECK-FULLFP16-NEXT: ret
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entry:
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%0 = fcmp ueq float %a, %b
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%vcmpd.i = sext i1 %0 to i32
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%vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0
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%1 = bitcast <1 x i32> %vecinit.i to <1 x float>
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ret <1 x float> %1
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}
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define <1 x float> @dup_v1i32_ugt(float %a, float %b) {
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; CHECK-NOFULLFP16-LABEL: dup_v1i32_ugt:
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; CHECK-NOFULLFP16: // %bb.0: // %entry
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; CHECK-NOFULLFP16-NEXT: fcmge s0, s1, s0
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; CHECK-NOFULLFP16-NEXT: mvn v0.8b, v0.8b
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; CHECK-NOFULLFP16-NEXT: ret
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;
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; CHECK-NONANS-LABEL: dup_v1i32_ugt:
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; CHECK-NONANS: // %bb.0: // %entry
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; CHECK-NONANS-NEXT: fcmgt s0, s0, s1
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; CHECK-NONANS-NEXT: ret
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;
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; CHECK-FULLFP16-LABEL: dup_v1i32_ugt:
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; CHECK-FULLFP16: // %bb.0: // %entry
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; CHECK-FULLFP16-NEXT: fcmge s0, s1, s0
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; CHECK-FULLFP16-NEXT: mvn v0.8b, v0.8b
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; CHECK-FULLFP16-NEXT: ret
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entry:
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%0 = fcmp ugt float %a, %b
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%vcmpd.i = sext i1 %0 to i32
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%vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0
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%1 = bitcast <1 x i32> %vecinit.i to <1 x float>
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ret <1 x float> %1
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}
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define <1 x float> @dup_v1i32_uge(float %a, float %b) {
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; CHECK-NOFULLFP16-LABEL: dup_v1i32_uge:
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; CHECK-NOFULLFP16: // %bb.0: // %entry
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; CHECK-NOFULLFP16-NEXT: fcmgt s0, s1, s0
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; CHECK-NOFULLFP16-NEXT: mvn v0.8b, v0.8b
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; CHECK-NOFULLFP16-NEXT: ret
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;
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; CHECK-NONANS-LABEL: dup_v1i32_uge:
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; CHECK-NONANS: // %bb.0: // %entry
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; CHECK-NONANS-NEXT: fcmge s0, s0, s1
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; CHECK-NONANS-NEXT: ret
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;
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; CHECK-FULLFP16-LABEL: dup_v1i32_uge:
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; CHECK-FULLFP16: // %bb.0: // %entry
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; CHECK-FULLFP16-NEXT: fcmgt s0, s1, s0
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; CHECK-FULLFP16-NEXT: mvn v0.8b, v0.8b
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; CHECK-FULLFP16-NEXT: ret
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entry:
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%0 = fcmp uge float %a, %b
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%vcmpd.i = sext i1 %0 to i32
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%vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0
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%1 = bitcast <1 x i32> %vecinit.i to <1 x float>
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ret <1 x float> %1
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}
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define <1 x float> @dup_v1i32_ult(float %a, float %b) {
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; CHECK-NOFULLFP16-LABEL: dup_v1i32_ult:
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; CHECK-NOFULLFP16: // %bb.0: // %entry
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; CHECK-NOFULLFP16-NEXT: fcmge s0, s0, s1
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; CHECK-NOFULLFP16-NEXT: mvn v0.8b, v0.8b
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; CHECK-NOFULLFP16-NEXT: ret
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;
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; CHECK-NONANS-LABEL: dup_v1i32_ult:
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; CHECK-NONANS: // %bb.0: // %entry
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; CHECK-NONANS-NEXT: fcmgt s0, s1, s0
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; CHECK-NONANS-NEXT: ret
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;
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; CHECK-FULLFP16-LABEL: dup_v1i32_ult:
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; CHECK-FULLFP16: // %bb.0: // %entry
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; CHECK-FULLFP16-NEXT: fcmge s0, s0, s1
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; CHECK-FULLFP16-NEXT: mvn v0.8b, v0.8b
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; CHECK-FULLFP16-NEXT: ret
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entry:
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%0 = fcmp ult float %a, %b
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%vcmpd.i = sext i1 %0 to i32
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%vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0
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%1 = bitcast <1 x i32> %vecinit.i to <1 x float>
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ret <1 x float> %1
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}
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define <1 x float> @dup_v1i32_ule(float %a, float %b) {
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; CHECK-NOFULLFP16-LABEL: dup_v1i32_ule:
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; CHECK-NOFULLFP16: // %bb.0: // %entry
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; CHECK-NOFULLFP16-NEXT: fcmgt s0, s0, s1
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; CHECK-NOFULLFP16-NEXT: mvn v0.8b, v0.8b
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; CHECK-NOFULLFP16-NEXT: ret
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;
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; CHECK-NONANS-LABEL: dup_v1i32_ule:
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; CHECK-NONANS: // %bb.0: // %entry
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; CHECK-NONANS-NEXT: fcmge s0, s1, s0
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; CHECK-NONANS-NEXT: ret
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;
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; CHECK-FULLFP16-LABEL: dup_v1i32_ule:
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; CHECK-FULLFP16: // %bb.0: // %entry
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; CHECK-FULLFP16-NEXT: fcmgt s0, s0, s1
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; CHECK-FULLFP16-NEXT: mvn v0.8b, v0.8b
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; CHECK-FULLFP16-NEXT: ret
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entry:
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%0 = fcmp ule float %a, %b
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%vcmpd.i = sext i1 %0 to i32
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%vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0
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%1 = bitcast <1 x i32> %vecinit.i to <1 x float>
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ret <1 x float> %1
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}
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define <1 x float> @dup_v1i32_une(float %a, float %b) {
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; CHECK-LABEL: dup_v1i32_une:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcmeq s0, s0, s1
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; CHECK-NEXT: mvn v0.8b, v0.8b
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp une float %a, %b
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%vcmpd.i = sext i1 %0 to i32
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%vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0
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%1 = bitcast <1 x i32> %vecinit.i to <1 x float>
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ret <1 x float> %1
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}
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define <1 x float> @dup_v1i32_uno(float %a, float %b) {
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; CHECK-LABEL: dup_v1i32_uno:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcmge s2, s0, s1
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; CHECK-NEXT: fcmgt s0, s1, s0
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; CHECK-NEXT: orr v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: mvn v0.8b, v0.8b
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp uno float %a, %b
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%vcmpd.i = sext i1 %0 to i32
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%vecinit.i = insertelement <1 x i32> poison, i32 %vcmpd.i, i64 0
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%1 = bitcast <1 x i32> %vecinit.i to <1 x float>
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ret <1 x float> %1
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}
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define <4 x float> @dup_v4i32(float %a, float %b) {
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; CHECK-LABEL: dup_v4i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcmge s0, s0, s1
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; CHECK-NEXT: dup v0.4s, v0.s[0]
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp oge float %a, %b
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%vcmpd.i = sext i1 %0 to i32
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%vecinit.i = insertelement <4 x i32> poison, i32 %vcmpd.i, i64 0
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%1 = bitcast <4 x i32> %vecinit.i to <4 x float>
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%2 = shufflevector <4 x float> %1, <4 x float> poison, <4 x i32> zeroinitializer
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ret <4 x float> %2
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}
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define <4 x float> @dup_v4i32_reversed(float %a, float %b) {
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; CHECK-LABEL: dup_v4i32_reversed:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcmgt s0, s1, s0
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; CHECK-NEXT: dup v0.4s, v0.s[0]
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp ogt float %b, %a
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%vcmpd.i = sext i1 %0 to i32
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%vecinit.i = insertelement <4 x i32> poison, i32 %vcmpd.i, i64 0
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%1 = bitcast <4 x i32> %vecinit.i to <4 x float>
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%2 = shufflevector <4 x float> %1, <4 x float> poison, <4 x i32> zeroinitializer
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ret <4 x float> %2
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}
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define <2 x double> @dup_v2i64(double %a, double %b) {
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; CHECK-LABEL: dup_v2i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcmgt d0, d0, d1
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; CHECK-NEXT: dup v0.2d, v0.d[0]
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp ogt double %a, %b
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%vcmpd.i = sext i1 %0 to i64
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%vecinit.i = insertelement <2 x i64> poison, i64 %vcmpd.i, i64 0
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%1 = bitcast <2 x i64> %vecinit.i to <2 x double>
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%2 = shufflevector <2 x double> %1, <2 x double> poison, <2 x i32> zeroinitializer
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ret <2 x double> %2
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}
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define <8 x half> @dup_v8i16(half %a, half %b) {
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; CHECK-NOFULLFP16-LABEL: dup_v8i16:
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; CHECK-NOFULLFP16: // %bb.0: // %entry
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; CHECK-NOFULLFP16-NEXT: fcvt s1, h1
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; CHECK-NOFULLFP16-NEXT: fcvt s0, h0
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; CHECK-NOFULLFP16-NEXT: fcmeq s0, s0, s1
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; CHECK-NOFULLFP16-NEXT: ret
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;
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; CHECK-NONANS-LABEL: dup_v8i16:
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; CHECK-NONANS: // %bb.0: // %entry
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; CHECK-NONANS-NEXT: fcvt s1, h1
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; CHECK-NONANS-NEXT: fcvt s0, h0
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; CHECK-NONANS-NEXT: fcmeq s0, s0, s1
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; CHECK-NONANS-NEXT: ret
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;
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; CHECK-FULLFP16-LABEL: dup_v8i16:
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; CHECK-FULLFP16: // %bb.0: // %entry
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; CHECK-FULLFP16-NEXT: fcmp h0, h1
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; CHECK-FULLFP16-NEXT: csetm w8, eq
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; CHECK-FULLFP16-NEXT: fmov s0, w8
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; CHECK-FULLFP16-NEXT: ret
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; FIXME: Could be replaced with fcmeq + dup but the type of the former is
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; promoted to i32 during selection and then the optimization does not apply.
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entry:
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%0 = fcmp oeq half %a, %b
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%vcmpd.i = sext i1 %0 to i16
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%vecinit.i = insertelement <8 x i16> poison, i16 %vcmpd.i, i64 0
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%1 = bitcast <8 x i16> %vecinit.i to <8 x half>
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ret <8 x half> %1
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}
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; Check that a mask is not generated for non-vectorized users.
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define i32 @mask_i32(float %a, float %b) {
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; CHECK-LABEL: mask_i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: csetm w0, eq
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; CHECK-NEXT: ret
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entry:
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%0 = fcmp oeq float %a, %b
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%vcmpd.i = sext i1 %0 to i32
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ret i32 %vcmpd.i
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}
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; Verify that a mask is not emitted when (allOnes, allZeros) are not the
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; operands for the SELECT_CC.
|
|
define i32 @bool_i32(float %a, float %b) {
|
|
; CHECK-LABEL: bool_i32:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcmp s0, s1
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|
; CHECK-NEXT: cset w0, eq
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|
; CHECK-NEXT: ret
|
|
entry:
|
|
%0 = fcmp oeq float %a, %b
|
|
%vcmpd.i = zext i1 %0 to i32
|
|
ret i32 %vcmpd.i
|
|
}
|