61510b51c3
This reverts commit 9c319d5bb40785c969d2af76535ca62448dfafa7. Some issues were discovered with the bootstrap builds, which seem like they were caused by this commit. I'm reverting to investigate.
149 lines
5.7 KiB
LLVM
149 lines
5.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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define <4 x half> @interleave2_v4f16(<2 x half> %vec0, <2 x half> %vec1) {
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; CHECK-LABEL: interleave2_v4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: zip1 v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%retval = call <4 x half> @llvm.vector.interleave2.v4f16(<2 x half> %vec0, <2 x half> %vec1)
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ret <4 x half> %retval
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}
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define <8 x half> @interleave2_v8f16(<4 x half> %vec0, <4 x half> %vec1) {
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; CHECK-SD-LABEL: interleave2_v8f16:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
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; CHECK-SD-NEXT: adrp x8, .LCPI1_0
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; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
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; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
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; CHECK-SD-NEXT: tbl v0.16b, { v0.16b }, v1.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: interleave2_v8f16:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
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; CHECK-GI-NEXT: zip1 v0.8h, v0.8h, v1.8h
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; CHECK-GI-NEXT: ret
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%retval = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %vec0, <4 x half> %vec1)
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ret <8 x half> %retval
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}
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define <16 x half> @interleave2_v16f16(<8 x half> %vec0, <8 x half> %vec1) {
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; CHECK-LABEL: interleave2_v16f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: zip1 v2.8h, v0.8h, v1.8h
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; CHECK-NEXT: zip2 v1.8h, v0.8h, v1.8h
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%retval = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %vec0, <8 x half> %vec1)
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ret <16 x half> %retval
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}
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define <4 x float> @interleave2_v4f32(<2 x float> %vec0, <2 x float> %vec1) {
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; CHECK-SD-LABEL: interleave2_v4f32:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
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; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
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; CHECK-SD-NEXT: rev64 v1.4s, v0.4s
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; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: interleave2_v4f32:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
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; CHECK-GI-NEXT: zip1 v0.4s, v0.4s, v1.4s
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; CHECK-GI-NEXT: ret
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%retval = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %vec0, <2 x float> %vec1)
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ret <4 x float> %retval
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}
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define <8 x float> @interleave2_v8f32(<4 x float> %vec0, <4 x float> %vec1) {
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; CHECK-LABEL: interleave2_v8f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: zip1 v2.4s, v0.4s, v1.4s
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; CHECK-NEXT: zip2 v1.4s, v0.4s, v1.4s
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%retval = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %vec0, <4 x float> %vec1)
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ret <8 x float> %retval
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}
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define <4 x double> @interleave2_v4f64(<2 x double> %vec0, <2 x double> %vec1) {
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; CHECK-LABEL: interleave2_v4f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: zip1 v2.2d, v0.2d, v1.2d
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; CHECK-NEXT: zip2 v1.2d, v0.2d, v1.2d
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%retval = call <4 x double>@llvm.vector.interleave2.v4f64(<2 x double> %vec0, <2 x double> %vec1)
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ret <4 x double> %retval
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}
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; Integers
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define <32 x i8> @interleave2_v32i8(<16 x i8> %vec0, <16 x i8> %vec1) {
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; CHECK-LABEL: interleave2_v32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: zip1 v2.16b, v0.16b, v1.16b
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; CHECK-NEXT: zip2 v1.16b, v0.16b, v1.16b
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%retval = call <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8> %vec0, <16 x i8> %vec1)
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ret <32 x i8> %retval
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}
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define <16 x i16> @interleave2_v16i16(<8 x i16> %vec0, <8 x i16> %vec1) {
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; CHECK-LABEL: interleave2_v16i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: zip1 v2.8h, v0.8h, v1.8h
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; CHECK-NEXT: zip2 v1.8h, v0.8h, v1.8h
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%retval = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %vec0, <8 x i16> %vec1)
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ret <16 x i16> %retval
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}
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define <8 x i32> @interleave2_v8i32(<4 x i32> %vec0, <4 x i32> %vec1) {
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; CHECK-LABEL: interleave2_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: zip1 v2.4s, v0.4s, v1.4s
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; CHECK-NEXT: zip2 v1.4s, v0.4s, v1.4s
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%retval = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %vec0, <4 x i32> %vec1)
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ret <8 x i32> %retval
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}
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define <4 x i64> @interleave2_v4i64(<2 x i64> %vec0, <2 x i64> %vec1) {
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; CHECK-LABEL: interleave2_v4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: zip1 v2.2d, v0.2d, v1.2d
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; CHECK-NEXT: zip2 v1.2d, v0.2d, v1.2d
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%retval = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %vec0, <2 x i64> %vec1)
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ret <4 x i64> %retval
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}
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; Float declarations
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declare <4 x half> @llvm.vector.interleave2.v4f16(<2 x half>, <2 x half>)
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declare <8 x half> @llvm.vector.interleave2.v8f16(<4 x half>, <4 x half>)
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declare <16 x half> @llvm.vector.interleave2.v16f16(<8 x half>, <8 x half>)
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declare <4 x float> @llvm.vector.interleave2.v4f32(<2 x float>, <2 x float>)
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declare <8 x float> @llvm.vector.interleave2.v8f32(<4 x float>, <4 x float>)
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declare <4 x double> @llvm.vector.interleave2.v4f64(<2 x double>, <2 x double>)
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; Integer declarations
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declare <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8>, <16 x i8>)
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declare <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16>, <8 x i16>)
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declare <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32>, <4 x i32>)
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declare <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64>, <2 x i64>)
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