862f42eedf
This was overlooked in 7d940432c46be83b8fcb5dbefee439585fa820cd - when inline assembly has multiple outputs, they are returned as members of a struct, and the `getAsmOperandType` needs to be called for each member of struct. The difference between this and the single-output case is that in the latter, there isn't a struct wrapping the outputs. I noticed this when trying to use the same mechanism in the RISC-V backend. Committing two tests: - One that shows a crash before this change, which is fixed by this change. - One (commented out) that shows a different crash with tied inputs/outputs. This is commented as it is not fixed by this change and needs more work in target-independent inline asm handling code.
138 lines
5.5 KiB
LLVM
138 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 -mattr=+ls64 -verify-machineinstrs -o - %s | FileCheck %s
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define void @load(ptr %output, ptr %addr) {
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; CHECK-LABEL: load:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: //APP
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; CHECK-NEXT: ld64b x2, [x1]
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; CHECK-NEXT: //NO_APP
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; CHECK-NEXT: stp x8, x9, [x0, #48]
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; CHECK-NEXT: stp x6, x7, [x0, #32]
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; CHECK-NEXT: stp x4, x5, [x0, #16]
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; CHECK-NEXT: stp x2, x3, [x0]
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; CHECK-NEXT: ret
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entry:
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%val = call i512 asm sideeffect "ld64b $0,[$1]", "=r,r,~{memory}"(ptr %addr)
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store i512 %val, ptr %output, align 8
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ret void
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}
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define void @store(ptr %input, ptr %addr) {
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; CHECK-LABEL: store:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ldp x8, x9, [x0, #48]
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; CHECK-NEXT: ldp x6, x7, [x0, #32]
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; CHECK-NEXT: ldp x4, x5, [x0, #16]
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; CHECK-NEXT: ldp x2, x3, [x0]
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; CHECK-NEXT: //APP
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; CHECK-NEXT: st64b x2, [x1]
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; CHECK-NEXT: //NO_APP
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; CHECK-NEXT: ret
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entry:
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%val = load i512, ptr %input, align 8
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call void asm sideeffect "st64b $0,[$1]", "r,r,~{memory}"(i512 %val, ptr %addr)
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ret void
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}
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define void @store2(ptr %in, ptr %addr) {
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; CHECK-LABEL: store2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sub sp, sp, #64
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: ldpsw x2, x3, [x0]
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; CHECK-NEXT: ldrsw x4, [x0, #16]
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; CHECK-NEXT: ldrsw x5, [x0, #64]
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; CHECK-NEXT: ldrsw x6, [x0, #100]
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; CHECK-NEXT: ldrsw x7, [x0, #144]
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; CHECK-NEXT: ldrsw x8, [x0, #196]
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; CHECK-NEXT: ldrsw x9, [x0, #256]
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; CHECK-NEXT: //APP
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; CHECK-NEXT: st64b x2, [x1]
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; CHECK-NEXT: //NO_APP
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; CHECK-NEXT: add sp, sp, #64
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; CHECK-NEXT: ret
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entry:
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%0 = load i32, ptr %in, align 4
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%conv = sext i32 %0 to i64
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%arrayidx1 = getelementptr inbounds i32, ptr %in, i64 1
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%1 = load i32, ptr %arrayidx1, align 4
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%conv2 = sext i32 %1 to i64
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%arrayidx4 = getelementptr inbounds i32, ptr %in, i64 4
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%2 = load i32, ptr %arrayidx4, align 4
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%conv5 = sext i32 %2 to i64
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%arrayidx7 = getelementptr inbounds i32, ptr %in, i64 16
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%3 = load i32, ptr %arrayidx7, align 4
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%conv8 = sext i32 %3 to i64
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%arrayidx10 = getelementptr inbounds i32, ptr %in, i64 25
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%4 = load i32, ptr %arrayidx10, align 4
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%conv11 = sext i32 %4 to i64
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%arrayidx13 = getelementptr inbounds i32, ptr %in, i64 36
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%5 = load i32, ptr %arrayidx13, align 4
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%conv14 = sext i32 %5 to i64
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%arrayidx16 = getelementptr inbounds i32, ptr %in, i64 49
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%6 = load i32, ptr %arrayidx16, align 4
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%conv17 = sext i32 %6 to i64
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%arrayidx19 = getelementptr inbounds i32, ptr %in, i64 64
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%7 = load i32, ptr %arrayidx19, align 4
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%conv20 = sext i32 %7 to i64
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%s.sroa.10.0.insert.ext = zext i64 %conv20 to i512
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%s.sroa.10.0.insert.shift = shl nuw i512 %s.sroa.10.0.insert.ext, 448
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%s.sroa.9.0.insert.ext = zext i64 %conv17 to i512
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%s.sroa.9.0.insert.shift = shl nuw nsw i512 %s.sroa.9.0.insert.ext, 384
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%s.sroa.9.0.insert.insert = or i512 %s.sroa.10.0.insert.shift, %s.sroa.9.0.insert.shift
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%s.sroa.8.0.insert.ext = zext i64 %conv14 to i512
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%s.sroa.8.0.insert.shift = shl nuw nsw i512 %s.sroa.8.0.insert.ext, 320
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%s.sroa.8.0.insert.insert = or i512 %s.sroa.9.0.insert.insert, %s.sroa.8.0.insert.shift
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%s.sroa.7.0.insert.ext = zext i64 %conv11 to i512
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%s.sroa.7.0.insert.shift = shl nuw nsw i512 %s.sroa.7.0.insert.ext, 256
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%s.sroa.7.0.insert.insert = or i512 %s.sroa.8.0.insert.insert, %s.sroa.7.0.insert.shift
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%s.sroa.6.0.insert.ext = zext i64 %conv8 to i512
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%s.sroa.6.0.insert.shift = shl nuw nsw i512 %s.sroa.6.0.insert.ext, 192
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%s.sroa.6.0.insert.insert = or i512 %s.sroa.7.0.insert.insert, %s.sroa.6.0.insert.shift
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%s.sroa.5.0.insert.ext = zext i64 %conv5 to i512
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%s.sroa.5.0.insert.shift = shl nuw nsw i512 %s.sroa.5.0.insert.ext, 128
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%s.sroa.4.0.insert.ext = zext i64 %conv2 to i512
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%s.sroa.4.0.insert.shift = shl nuw nsw i512 %s.sroa.4.0.insert.ext, 64
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%s.sroa.4.0.insert.mask = or i512 %s.sroa.6.0.insert.insert, %s.sroa.5.0.insert.shift
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%s.sroa.0.0.insert.ext = zext i64 %conv to i512
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%s.sroa.0.0.insert.mask = or i512 %s.sroa.4.0.insert.mask, %s.sroa.4.0.insert.shift
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%s.sroa.0.0.insert.insert = or i512 %s.sroa.0.0.insert.mask, %s.sroa.0.0.insert.ext
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call void asm sideeffect "st64b $0,[$1]", "r,r,~{memory}"(i512 %s.sroa.0.0.insert.insert, ptr %addr)
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ret void
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}
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define void @multi_output(ptr %addr) {
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; CHECK-LABEL: multi_output:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: //APP
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; CHECK-NEXT: ld64b x0, [x0]
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; CHECK-NEXT: mov x8, x0
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; CHECK-NEXT: //NO_APP
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; CHECK-NEXT: stp x6, x7, [x8, #48]
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; CHECK-NEXT: stp x4, x5, [x8, #32]
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; CHECK-NEXT: stp x2, x3, [x8, #16]
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; CHECK-NEXT: stp x0, x1, [x8]
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; CHECK-NEXT: ret
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entry:
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%val = call { i512, ptr } asm sideeffect "ld64b $0, [$2]; mov $1, $2", "=r,=r,r,~{memory}"(ptr %addr)
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%val0 = extractvalue { i512, ptr } %val, 0
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%val1 = extractvalue { i512, ptr } %val, 1
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store i512 %val0, ptr %val1, align 8
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ret void
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}
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; FIXME: This case still crashes in RegsForValue::AddInlineAsmOperands without
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; additional changes. I believe this is a bug in target-independent code, that
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; is worked around in the RISC-V and SystemZ backends, but should almost
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; certainly be fixed instead.
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; define void @tied_constraints(ptr %addr) {
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; entry:
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; %in = load i512, ptr %addr, align 8
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; %val = call { i512, ptr } asm sideeffect "nop", "=r,=r,0,1,~{memory}"(i512 %in, ptr %addr)
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; %val0 = extractvalue { i512, ptr } %val, 0
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; %val1 = extractvalue { i512, ptr } %val, 1
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; store i512 %val0, ptr %val1, align 8
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; ret void
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; }
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