cc82f1290a
Updated according to the Software Optimization Guide for Arm® Cortex®‑A510 Core Revision: r1p3 Issue 6.0.
69 lines
2.8 KiB
LLVM
69 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefix=VBITS_GE_256
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; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefix=VBITS_GE_256
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target triple = "aarch64-unknown-linux-gnu"
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define void @build_vector_7_inc1_v32i8(ptr %a) #0 {
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; VBITS_GE_256-LABEL: build_vector_7_inc1_v32i8:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: index z0.b, #7, #1
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; VBITS_GE_256-NEXT: ptrue p0.b, vl32
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; VBITS_GE_256-NEXT: st1b { z0.b }, p0, [x0]
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; VBITS_GE_256-NEXT: ret
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store <32 x i8> <i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38>, ptr %a, align 1
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ret void
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}
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define void @build_vector_0_inc2_v16i16(ptr %a) #0 {
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; VBITS_GE_256-LABEL: build_vector_0_inc2_v16i16:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: index z0.h, #0, #2
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; VBITS_GE_256-NEXT: ptrue p0.h, vl16
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; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x0]
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; VBITS_GE_256-NEXT: ret
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store <16 x i16> <i16 0, i16 2, i16 4, i16 6, i16 8, i16 10, i16 12, i16 14, i16 16, i16 18, i16 20, i16 22, i16 24, i16 26, i16 28, i16 30>, ptr %a, align 2
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ret void
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}
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; Negative const stride.
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define void @build_vector_0_dec3_v8i32(ptr %a) #0 {
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; VBITS_GE_256-LABEL: build_vector_0_dec3_v8i32:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: index z0.s, #0, #-3
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; VBITS_GE_256-NEXT: ptrue p0.s, vl8
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; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x0]
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; VBITS_GE_256-NEXT: ret
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store <8 x i32> <i32 0, i32 -3, i32 -6, i32 -9, i32 -12, i32 -15, i32 -18, i32 -21>, ptr %a, align 4
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ret void
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}
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; Constant stride that's too big to be directly encoded into the index.
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define void @build_vector_minus2_dec32_v4i64(ptr %a) #0 {
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; VBITS_GE_256-LABEL: build_vector_minus2_dec32_v4i64:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: mov x8, #-32 // =0xffffffffffffffe0
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; VBITS_GE_256-NEXT: ptrue p0.d, vl4
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; VBITS_GE_256-NEXT: index z0.d, #-2, x8
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; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0]
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; VBITS_GE_256-NEXT: ret
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store <4 x i64> <i64 -2, i64 -34, i64 -66, i64 -98>, ptr %a, align 8
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ret void
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}
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; Constant but not a sequence.
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define void @build_vector_no_stride_v4i64(ptr %a) #0 {
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; VBITS_GE_256-LABEL: build_vector_no_stride_v4i64:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.d, vl4
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; VBITS_GE_256-NEXT: adrp x8, .LCPI4_0
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; VBITS_GE_256-NEXT: add x8, x8, :lo12:.LCPI4_0
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; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x8]
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; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x0]
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; VBITS_GE_256-NEXT: ret
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store <4 x i64> <i64 0, i64 4, i64 1, i64 8>, ptr %a, align 8
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ret void
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}
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attributes #0 = { "target-features"="+sve" }
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