Hal Finkel bc2ee4c4e6 PPC: Combine duplicate (offset) lvsl Altivec intrinsics ...

The lvsl permutation control instruction is a function only of the alignment of
the pointer operand (relative to the 16-byte natural alignment of Altivec
vectors). As a result, multiple lvsl intrinsics where the operands differ by a
multiple of 16 can be combined.

llvm-svn: 182708

2013-05-25 04:05:05 +00:00

..

AArch64

Track IR ordering of SelectionDAG nodes 3/4.

2013-05-25 03:08:10 +00:00

ARM

Track IR ordering of SelectionDAG nodes 4/4.

2013-05-25 03:26:51 +00:00

CPP

test commit: remove blank line.

2013-03-14 05:43:59 +00:00

Generic

Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.

2013-05-21 14:37:16 +00:00

Hexagon

Hexagon: Pass to replace tranfer/copy instructions into combine instruction

2013-05-14 18:54:06 +00:00

Inputs

Revert "Adding DIImportedModules to DIScopes."

2013-03-28 02:44:59 +00:00

MBlaze

Remove unnecessary leading comment characters in lit-only file

2013-03-18 22:08:16 +00:00

Mips

Track IR ordering of SelectionDAG nodes 4/4.

2013-05-25 03:26:51 +00:00

MSP430

DAGCombiner: Simplify inverted bit tests

2013-05-08 06:44:42 +00:00

NVPTX

[NVPTX] Add @llvm.nvvm.sqrt.f() intrinsic

2013-05-21 16:51:30 +00:00

PowerPC

PPC: Combine duplicate (offset) lvsl Altivec intrinsics

2013-05-25 04:05:05 +00:00

R600

R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg

2013-05-23 18:26:42 +00:00

SI

Add R600 backend

2012-12-11 21:25:42 +00:00

SPARC

Also expand 64-bit bitcasts.

2013-05-20 01:01:43 +00:00

SystemZ

[SystemZ] Tighten branch tests

2013-05-21 08:53:17 +00:00

Thumb

LocalStackSlotAllocation improvements

2013-04-30 20:04:37 +00:00

Thumb2

Fix ARM FastISel tests, as a first step to enabling ARM FastISel

2013-05-14 16:26:38 +00:00

X86

Track IR ordering of SelectionDAG nodes 4/4.

2013-05-25 03:26:51 +00:00

XCore

[XCore] Fix handling of functions where only the LR is spilled.

2013-05-09 16:43:42 +00:00