Matt Arsenault bd2dca0f74 AMDGPU: Use hex floats instead of ugly bitcasting

2023-07-17 19:54:04 -04:00

..

AArch64

[SVE][CodeGen] Improve codegen for some zero-extends of masked loads

2023-07-17 08:19:27 +00:00

AMDGPU

AMDGPU: Use hex floats instead of ugly bitcasting

2023-07-17 19:54:04 -04:00

ARC

…

ARM

[ARM] Adjust strd/ldrd codegen alignment requirements

2023-07-14 12:54:18 -07:00

AVR

…

BPF

[llvm] Remove explicit -opaque-pointers flag from tests (NFC)

2023-07-12 14:35:55 +02:00

CSKY

[CSKY] Optimize conditional select with CLRT/CLRF

2023-07-04 15:22:18 +08:00

DirectX

…

Generic

…

Hexagon

[llvm] Remove explicit -opaque-pointers flag from tests (NFC)

2023-07-12 14:35:55 +02:00

Inputs

…

Lanai

…

LoongArch

[XRay] Add initial support for loongarch64

2023-07-14 09:27:13 +08:00

M68k

[M68k][MC] Add support for 32 bit register-register multiply/divide

2023-06-29 21:39:41 -07:00

Mips

[Mips] Set setMaxAtomicSizeInBitsSupported

2023-07-15 17:29:25 -04:00

MIR

Revert "[CodeGen] Store SP adjustment in MachineBasicBlock. NFCI."

2023-07-13 14:25:39 +01:00

MLRegalloc

…

MSP430

…

NVPTX

Fix shr/and pair replace with bfe

2023-07-11 14:43:35 +01:00

PowerPC

[AIX][TLS] Account for local-exec accesses in XCOFFObjectWriter

2023-07-17 12:15:44 -05:00

RISCV

[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.

2023-07-17 08:58:29 -07:00

SPARC

…

SPIRV

…

SystemZ

[NFC] Autogenerate CodeGen/SystemZ/int-{uadd,sub}-0*.ll

2023-07-05 20:14:43 +00:00

Thumb

[ARM] make execute only long call test checks more robust

2023-07-04 10:51:48 +01:00

Thumb2

[ARM] Adjust strd/ldrd codegen alignment requirements

2023-07-14 12:54:18 -07:00

VE

…

WebAssembly

[MachineLICM] Handle Subloops

2023-07-12 16:32:14 +01:00

WinCFGuard

…

WinEH

…

X86

[X86] Regenerate tail-call-casts.ll test coverage

2023-07-17 17:58:37 +01:00

XCore

…