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llvm-project/llvm/test/CodeGen/RISCV/rvv
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Yingchi Long 0359c19e8f
[RISCV][VP] support vp.reduce.mul by ExpandVectorPredication 
Most of VP intrinsics are implemented in RISC-V backends, but
vp.reduce.mul (element length > 1) does not yet. Legalizes vp.reduce.mul
using ExpandVectorPredication Pass.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D139721
2022-12-17 10:49:47 +08:00
..
abs-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
access-fixed-objects-by-rvv.ll
[RISCV] Generate .cfi_def_cfa_expression for RVV stack adjustment
2022-12-06 12:45:59 +03:00
active_lane_mask.ll
[RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility.
2022-12-06 10:31:17 -08:00
addi-rvv-stack-object.mir
[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
2022-07-03 20:18:13 +08:00
addi-scalable-offset.mir
[RISCV] Share code for fixed offsets adjustRegs (thus materializing fewer constants)
2022-11-30 09:28:29 -08:00
aliases.mir
…
allocate-lmul-2-4-8.ll
[RISCV] Extend use of SHXADD instructions in RVV spill/reload code.
2022-07-18 10:53:19 +08:00
allone-masked-to-unmasked.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
bitreverse-sdnode.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
bitreverse-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
bswap-sdnode.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
bswap-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
calling-conv-fastcc.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
calling-conv.ll
[MachineFrameInfo][RISCV] Call ensureStackAlignment for objects created with scalable vector stack id.
2022-10-20 14:05:46 -07:00
ceil-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
cmp-folds.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
combine-sats.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
combine-splats.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
combine-store-fp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
common-shuffle-patterns.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
commuted-op-indices-regression.mir
[RISCV] Add MIR comments for VecPolicy operands
2022-09-13 15:36:33 -07:00
constant-folding-crash.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
constant-folding.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
ctlz-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
ctpop-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
ctpop-vp.ll
[VP][RISCV] Add vp.ctpop and RISC-V support.
2022-12-14 09:47:44 +08:00
cttz-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
debug-info-rvv-dbg-value.mir
…
emergency-slot.mir
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
extload-truncstore.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
extract-subvector.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
extractelt-fp.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
extractelt-i1.ll
[RISCV] Add test for extract the first element from mask vector.
2022-12-08 15:44:02 +08:00
extractelt-int-rv32.ll
[MachineFrameInfo][RISCV] Call ensureStackAlignment for objects created with scalable vector stack id.
2022-10-20 14:05:46 -07:00
extractelt-int-rv64.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
fceil-sdnode.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
ffloor-sdnode.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
fixed-vector-fpext-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vector-fptrunc-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vector-inttoptr-ptrtoint.ll
[VP] Add support for vp.inttoptr & vp.ptrtoint
2022-11-18 10:42:24 +08:00
fixed-vector-segN-load.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vector-shuffle-reverse.ll
[RISCV][InsertVSETVLI] Mutate prior vsetvli AVL if doing so allows us to remove a toggle
2022-12-15 07:32:28 -08:00
fixed-vector-strided-load-store-asm.ll
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
2022-12-01 11:09:38 -08:00
fixed-vector-strided-load-store-negative.ll
…
fixed-vector-strided-load-store.ll
…
fixed-vector-trunc-vp-mask.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vector-trunc-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-abs.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-bitcast-large-vector.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-bitcast.ll
[RISCV] Optimize i64 insertelt on RV32.
2022-10-28 10:23:19 -07:00
fixed-vectors-bitreverse-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-bitreverse.ll
[TargetLowering][RISCV][ARM][AArch64][Mips] Reduce the number of AND mask constants used by BSWAP expansion.
2022-11-15 14:36:01 -08:00
fixed-vectors-bswap-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-bswap.ll
[TargetLowering][RISCV][ARM][AArch64][Mips] Reduce the number of AND mask constants used by BSWAP expansion.
2022-11-15 14:36:01 -08:00
fixed-vectors-calling-conv-fastcc.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-calling-conv.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-ceil-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-ctlz.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-ctpop-vp.ll
[VP][RISCV] Add vp.ctpop and RISC-V support.
2022-12-14 09:47:44 +08:00
fixed-vectors-ctpop.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-cttz.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-elen.ll
[RISCV] Add ADD to getRegAllocationHints to improve to improve use of c.add.
2022-11-25 08:59:27 -08:00
fixed-vectors-emergency-slot.mir
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-extload-truncstore.ll
[RISCV] Cleanup some vector tests. NFC
2022-10-06 10:51:39 -07:00
fixed-vectors-extract-i1.ll
[RISCV] Add test for extract the first element from mask vector.
2022-12-08 15:44:02 +08:00
fixed-vectors-extract-subvector.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-extract.ll
[RISCV] Use vmv.v.i for insertion into lane 0 of undef vector when profitable
2022-12-13 07:54:46 -08:00
fixed-vectors-floor-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-fmf.ll
[RISCV] Copy SDNodeFlags in lowerToScalableOp.
2022-08-18 20:42:59 -07:00
fixed-vectors-fp2i-sat.ll
[RISCV][CodeGen][SelectionDAG] Recursively check hasAllNBitUsers for logical machine opcodes
2022-12-14 15:15:30 -08:00
fixed-vectors-fp2i.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
fixed-vectors-fp-bitcast.ll
[RISCV] Optimize i64 insertelt on RV32.
2022-10-28 10:23:19 -07:00
fixed-vectors-fp-buildvec.ll
[RISCV] Adjust RV64I data layout by using n32:64 in layout string
2022-10-28 08:27:03 -07:00
fixed-vectors-fp-conv.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
fixed-vectors-fp-interleave.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-fp-setcc.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-fp-shuffles.ll
[RISCV] Lower VECTOR_SHUFFLE to VSLIDEDOWN_VL.
2022-10-18 08:58:39 -07:00
fixed-vectors-fp-splat.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-fp-vrgather.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-fp.ll
[RISCV] Support F16 vectors with Zfhmin+Zvfh.
2022-12-07 19:14:11 -08:00
fixed-vectors-fptosi-vp-mask.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
fixed-vectors-fptosi-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-fptoui-vp-mask.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
fixed-vectors-fptoui-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-fround.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
fixed-vectors-froundeven.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
fixed-vectors-fshr-fshl-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-i2fp.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
fixed-vectors-insert-i1.ll
[RISCV] Avoid generate large LMUL vmv.s.x or fvmv.s.f
2022-12-14 10:53:34 -08:00
fixed-vectors-insert-subvector.ll
[MachineFrameInfo][RISCV] Call ensureStackAlignment for objects created with scalable vector stack id.
2022-10-20 14:05:46 -07:00
fixed-vectors-insert.ll
[RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.
2022-11-30 10:28:57 -08:00
fixed-vectors-int-buildvec.ll
[RISCV] Use vmv.v.i for insertion into lane 0 of undef vector when profitable
2022-12-13 07:54:46 -08:00
fixed-vectors-int-exttrunc.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-int-interleave.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-int-setcc.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-int-shuffles.ll
[RISCV] Avoid generate large LMUL vmv.s.x or fvmv.s.f
2022-12-14 10:53:34 -08:00
fixed-vectors-int-splat.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
fixed-vectors-int-vrgather.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
fixed-vectors-int.ll
[RISCV] Use vmv.v.i for insertion into lane 0 of undef vector when profitable
2022-12-13 07:54:46 -08:00
fixed-vectors-marith-vp.ll
[RISCV] Cleanup some vector tests. NFC
2022-10-06 10:51:39 -07:00
fixed-vectors-mask-buildvec.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-mask-load-store.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-mask-logic.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-mask-splat.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-masked-gather.ll
[RISCV][InsertVSETVLI] Mutate prior vsetvli AVL if doing so allows us to remove a toggle
2022-12-15 07:32:28 -08:00
fixed-vectors-masked-load-fp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-masked-load-int.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-masked-scatter.ll
[RISCV] Add ANDI to getRegAllocationHints.
2022-11-30 20:59:02 -08:00
fixed-vectors-masked-store-fp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-masked-store-int.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-nearbyint-vp.ll
[VP][RISCV] Add vp.nearbyint and RISC-V support.
2022-11-16 14:05:35 +08:00
fixed-vectors-peephole-vmerge-vops.ll
[RISCV] Cleanup some vector tests. NFC
2022-10-06 10:51:39 -07:00
fixed-vectors-reduction-fp-vp.ll
[RISCV] Allow fractional LMUL for reduction start value
2022-12-12 09:08:21 -08:00
fixed-vectors-reduction-fp.ll
[RISCV][InsertVSETVLI] Mutate prior vsetvli AVL if doing so allows us to remove a toggle
2022-12-15 07:32:28 -08:00
fixed-vectors-reduction-int-vp.ll
[RISCV][VP] support vp.reduce.mul by ExpandVectorPredication
2022-12-17 10:49:47 +08:00
fixed-vectors-reduction-int.ll
[RISCV][InsertVSETVLI] Mutate prior vsetvli AVL if doing so allows us to remove a toggle
2022-12-15 07:32:28 -08:00
fixed-vectors-reduction-mask-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-rint-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-round-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-roundeven-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-roundtozero-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-select-fp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-select-int.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-setcc-fp-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-setcc-int-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-setcc-int-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-sext-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-sext-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-shufflevector-vnsrl.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-sitofp-vp-mask.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
fixed-vectors-sitofp-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-stepvector.ll
[RISCV] Use vmv.v.i for insertion into lane 0 of undef vector when profitable
2022-12-13 07:54:46 -08:00
fixed-vectors-store-merge-crash.ll
…
fixed-vectors-strided-vpload.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-strided-vpstore.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-uitofp-vp-mask.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
fixed-vectors-uitofp-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-unaligned.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
fixed-vectors-vadd-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vadd-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-vand-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vcopysign-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-vdiv-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vdivu-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vfabs-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-vfadd-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vfdiv-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vfma-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-vfmacc-vp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vfmax-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-vfmax.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vfmin-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-vfmin.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vfmsac-vp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vfmul-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vfmuladd-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-vfneg-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-vfnmacc-vp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vfnmsac-vp.ll
[RISCV] Use fixed vector types in fixed-vectors-vfnmsac-vp.ll. NFC
2022-10-06 11:02:13 -07:00
fixed-vectors-vfrdiv-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vfrsub-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vfsqrt-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-vfsub-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vfwadd.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-vfwmacc.ll
[RISCV] Cleanup some vector tests. NFC
2022-10-06 10:51:39 -07:00
fixed-vectors-vfwmul.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-vfwsub.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-vmacc-vp.ll
[RISCV] Add isel patterns for vmacc, vnmsac.
2022-10-12 09:19:01 +08:00
fixed-vectors-vmax-vp.ll
[VP] Teach isVPBinaryOp to recognize vp.smin/smax/umin/umax/minnum/maxnum.
2022-10-20 07:21:13 +08:00
fixed-vectors-vmaxu-vp.ll
[VP] Teach isVPBinaryOp to recognize vp.smin/smax/umin/umax/minnum/maxnum.
2022-10-20 07:21:13 +08:00
fixed-vectors-vmin-vp.ll
[VP] Teach isVPBinaryOp to recognize vp.smin/smax/umin/umax/minnum/maxnum.
2022-10-20 07:21:13 +08:00
fixed-vectors-vminu-vp.ll
[VP] Teach isVPBinaryOp to recognize vp.smin/smax/umin/umax/minnum/maxnum.
2022-10-20 07:21:13 +08:00
fixed-vectors-vmul-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vmul-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vnmsac-vp.ll
[RISCV] Add isel patterns for vmacc, vnmsac.
2022-10-12 09:19:01 +08:00
fixed-vectors-vnsra-vnsrl.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vor-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vpgather.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-vpload.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-vpmerge.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-vpscatter.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-vpstore.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
fixed-vectors-vreductions-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vrem-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vremu-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vrsub-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vsadd.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vsaddu.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vselect-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
fixed-vectors-vselect.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vshl-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vsra-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vsrl-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vssub.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vssubu.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vsub-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vsub-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-vw-web-simplification.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vwadd.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-vwaddu.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-vwmacc.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vwmaccsu.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vwmaccu.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vwmaccus.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-vwmul.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-vwmulsu.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-vwmulu.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-vwsub.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-vwsubu.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fixed-vectors-vxor-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
fixed-vectors-zext-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fixed-vectors-zext-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
floor-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fold-binary-reduce.ll
[RISCV] Reuse VL (if non-zero) when building single element vector for start of reduction chain
2022-12-13 12:16:26 -08:00
fptosi-sat.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
fptoui-sat.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
frameindex-addr.ll
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
fround-sdnode.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
froundeven-sdnode.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
fshr-fshl-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
fshr-fshl.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
ftrunc-sdnode.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
get-vlen-debugloc.mir
[RISCV] Generate .cfi_def_cfa_expression for RVV stack adjustment
2022-12-06 12:45:59 +03:00
implicit-def-copy.ll
[RISCV] Add MIR comments for VecPolicy operands
2022-09-13 15:36:33 -07:00
inline-asm.ll
…
insert-subvector.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
insertelt-fp.ll
[RISCV] Avoid generate large LMUL vmv.s.x or fvmv.s.f
2022-12-14 10:53:34 -08:00
insertelt-i1.ll
[RISCV] Avoid generate large LMUL vmv.s.x or fvmv.s.f
2022-12-14 10:53:34 -08:00
insertelt-int-rv32.ll
[RISCV] Avoid generate large LMUL vmv.s.x or fvmv.s.f
2022-12-14 10:53:34 -08:00
insertelt-int-rv64.ll
[RISCV] Avoid generate large LMUL vmv.s.x or fvmv.s.f
2022-12-14 10:53:34 -08:00
interleave-crash.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
large-rvv-stack-size.mir
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
legalize-load-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
legalize-scalable-vectortype.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
legalize-store-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
load-add-store-8.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
load-add-store-16.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
load-add-store-32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
load-add-store-64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
load-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
localvar.ll
[RISCV] Generate .cfi_def_cfa_expression for RVV stack adjustment
2022-12-06 12:45:59 +03:00
marith-vp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
mask-exts-truncs-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
mask-exts-truncs-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
mask-reg-alloc.mir
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
masked-load-fp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
masked-load-int.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
masked-store-fp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
masked-store-int.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
masked-tama.ll
[RISCV][InsertVSETVLI] Treat mask policy as undemanded if usesMaskPolicy is false
2022-10-06 07:20:16 -07:00
masked-tamu.ll
…
masked-tuma.ll
…
masked-tumu.ll
…
masked-vslide1down-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
memory-args.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
mgather-sdnode.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
mscatter-combine.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
mscatter-sdnode.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
named-vector-shuffle-reverse.ll
[MachineFrameInfo][RISCV] Call ensureStackAlignment for objects created with scalable vector stack id.
2022-10-20 14:05:46 -07:00
nearbyint-vp.ll
[VP][RISCV] Add vp.nearbyint and RISC-V support.
2022-11-16 14:05:35 +08:00
no-reserved-frame.ll
…
pass-fast-math-flags-sdnode.ll
[RISCV] Add MIR comments for VecPolicy operands
2022-09-13 15:36:33 -07:00
pr52475.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
reg-alloc-reserve-bp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
reg-coalescing.mir
…
regalloc-fast-crash.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
rint-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
round-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
roundeven-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
roundtozero-vp.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
rv32-spill-vector-csr.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
rv32-spill-vector.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
rv32-spill-zvlsseg.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
rv32-vsetvli-intrinsics.ll
…
rv64-spill-vector-csr.ll
[RISCV] Optimize scalable frame setup when VLEN is precisely known
2022-11-18 15:30:39 -08:00
rv64-spill-vector.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
rv64-spill-zvlsseg.ll
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
rv64-vsetvli-intrinsics.ll
…
rvv-args-by-mem.ll
[MachineFrameInfo][RISCV] Call ensureStackAlignment for objects created with scalable vector stack id.
2022-10-20 14:05:46 -07:00
rvv-framelayout.ll
…
rvv-out-arguments.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
rvv-peephole-vmerge-vops-mir.ll
[RISCV] Support peephole optimization to fold vmerge.vvm that has tail agnostic policy and unmasked intrinsics.
2022-09-21 10:56:37 +08:00
rvv-peephole-vmerge-vops.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
rvv-stack-align.mir
[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
2022-07-03 20:18:13 +08:00
rvv-vmerge-to-vadd.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
rvv-vscale.i32.ll
…
rvv-vscale.i64.ll
[RISCV] Refine known bits for READ_VLENB
2022-06-28 15:42:14 -07:00
saddo-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
scalar-stack-align.ll
[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
2022-07-03 20:18:13 +08:00
select-fp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
select-int.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
select-sra.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
setcc-fp-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
setcc-fp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
setcc-int-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
setcc-int-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
setcc-integer.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
sink-splat-operands.ll
[RISCV] Use register allocation hints to improve use of compressed instructions.
2022-11-25 08:39:44 -08:00
smulo-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
splat-vectors.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
splats-with-mixed-vl.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
sshl_sat_vec.ll
[LegalizeVectorOps][X86][RISCV] Expand vector S/USHLSAT instead of unrolling.
2022-10-27 09:09:36 -07:00
stack-coloring-scalablevec.mir
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
stepvector.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
strided-load-store-intrinsics.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
strided-load-store.ll
[RISCV] Pattern match scalable strided load/store
2022-09-24 17:41:58 -07:00
strided-vpload.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
strided-vpstore.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
tail-agnostic-impdef-copy.mir
[RISCV] Add MIR comments for VecPolicy operands
2022-09-13 15:36:33 -07:00
umulo-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
unaligned-loads-stores.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
undef-vp-ops.ll
…
unmasked-ta.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
unmasked-tu.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
urem-seteq-vec.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
ushl_sat_vec.ll
[LegalizeVectorOps][X86][RISCV] Expand vector S/USHLSAT instead of unrolling.
2022-10-27 09:09:36 -07:00
vaadd.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vaaddu.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vadc.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vadd-sdnode.ll
[RISCV] Fold vector binary operatrion into select with identity constant.
2022-12-06 11:19:31 +08:00
vadd-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vadd.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vand-sdnode.ll
[RISCV] Fold vector binary operatrion into select with identity constant.
2022-12-06 11:19:31 +08:00
vand-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vand.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
variant-cc.ll
[RISCV] Emit .variant_cc directives for vector function calls.
2022-12-16 13:51:39 +08:00
vasub.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vasubu.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vcompress.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vcopysign-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vcpop.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vdiv-sdnode.ll
[RISCV][test] Add pre-commit test for D131551.
2022-12-06 10:38:25 +08:00
vdiv-vp.ll
[SDAG] Allow scalable vectors in ComputeNumSignBits (try 2)
2022-11-29 08:25:05 -08:00
vdiv.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vdivu-sdnode.ll
[RISCV][test] Add pre-commit test for D131551.
2022-12-06 10:38:25 +08:00
vdivu-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vdivu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vector-splice.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vexts-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfabs-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfabs-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vfadd-sdnode.ll
[RISCV] Fold vector binary operatrion into select with identity constant.
2022-12-06 11:19:31 +08:00
vfadd-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vfadd.ll
[RISCV] Support F16 vectors with Zfhmin+Zvfh.
2022-12-07 19:14:11 -08:00
vfclass.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfcopysign-sdnode.ll
[DAGCombiner] Scalarize extend/truncate for splat vector.
2022-12-12 14:53:10 +08:00
vfcvt-f-x.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfcvt-f-xu.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfcvt-rtz-x-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfcvt-rtz-xu-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfcvt-x-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfcvt-xu-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfdiv-sdnode.ll
[RISCV][test] Add pre-commit test for D131551.
2022-12-06 10:38:25 +08:00
vfdiv-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vfdiv.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfirst.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfma-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
vfmacc-vp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmacc.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmadd-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmadd.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmax-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmax-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vfmax.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmerge.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmin-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmin-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vfmin.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmsac-vp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmsac.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmsub-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmsub.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmul-sdnode.ll
[RISCV][test] Add pre-commit test for D131551.
2022-12-06 10:38:25 +08:00
vfmul-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vfmul.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmuladd-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
vfmv.f.s.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmv.s.f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfmv.v.f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfncvt-f-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfncvt-f-x.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfncvt-f-xu.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfncvt-rod-f-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfncvt-rtz-x-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfncvt-rtz-xu-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfncvt-x-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfncvt-xu-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfneg-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfneg-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vfnmacc-vp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfnmacc.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfnmadd-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfnmadd.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfnmsac-vp.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfnmsac.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfnmsub-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfnmsub.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfpext-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfpext-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vfptoi-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfptosi-vp-mask.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
vfptosi-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
vfptoui-vp-mask.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
vfptoui-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
vfptrunc-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfptrunc-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
vfrdiv-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vfrdiv.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfrec7.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfredmax.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfredmin.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfredosum.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfredusum.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfrsqrt7.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfrsub-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vfrsub.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfsgnj.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfsgnjn.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfsgnjx.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfslide1down.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfslide1up.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfsqrt-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfsqrt-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vfsqrt.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfsub-sdnode.ll
[RISCV] Fold vector binary operatrion into select with identity constant.
2022-12-06 11:19:31 +08:00
vfsub-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vfsub.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwadd-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwadd.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwadd.w.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwcvt-f-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwcvt-f-x.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwcvt-f-xu.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwcvt-rtz-x-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwcvt-rtz-xu-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwcvt-x-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwcvt-xu-f.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwmacc-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwmacc.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwmsac.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwmul-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwmul.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwnmacc.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwnmsac.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwredosum.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwredusum.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwsub-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwsub.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vfwsub.w.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vid.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
viota.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vitofp-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vle_vid-vfcvt.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vle.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vleff-vlseg2ff-output.ll
[RISCV] Add MIR comments for VecPolicy operands
2022-09-13 15:36:33 -07:00
vleff.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vlm.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vloxei-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vloxei.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vloxseg-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vloxseg-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vlse.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vlseg-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vlseg-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vlsegff-rv32-dead.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vlsegff-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vlsegff-rv64-dead.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vlsegff-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vlsseg-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vlsseg-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vluxei-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vluxei.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vluxseg-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vluxseg-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmacc-vp.ll
[RISCV] Add isel patterns for vmacc, vnmsac.
2022-10-12 09:19:01 +08:00
vmacc.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmadc.carry.in.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmadc.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmadd-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmadd.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmand.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmandn.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmarith-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmax-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmax-vp.ll
[SDAG] Allow scalable vectors in ComputeNumSignBits (try 2)
2022-11-29 08:25:05 -08:00
vmax.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmaxu-sdnode.ll
[RISCV][test] Add pre-commit test for D131551.
2022-12-06 10:38:25 +08:00
vmaxu-vp.ll
[VP] Teach isVPBinaryOp to recognize vp.smin/smax/umin/umax/minnum/maxnum.
2022-10-20 07:21:13 +08:00
vmaxu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmclr.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmerge.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmfeq.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmfge.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmfgt.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmfle.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmflt.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmfne.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmin-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmin-vp.ll
[SDAG] Allow scalable vectors in ComputeNumSignBits (try 2)
2022-11-29 08:25:05 -08:00
vmin.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vminu-sdnode.ll
[RISCV][test] Add pre-commit test for D131551.
2022-12-06 10:38:25 +08:00
vminu-vp.ll
[VP] Teach isVPBinaryOp to recognize vp.smin/smax/umin/umax/minnum/maxnum.
2022-10-20 07:21:13 +08:00
vminu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmnand.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmnor.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmor.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmorn.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmsbc.borrow.in.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsbc.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsbf.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmseq.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmset.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmsge.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsgeu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsgt.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsgtu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsif.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmsle.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsleu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmslt.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsltu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsne.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vmsof.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmul-sdnode.ll
[RISCV] Fold vector binary operatrion into select with identity constant.
2022-12-06 11:19:31 +08:00
vmul-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vmul.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmulh-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmulh.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmulhsu.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmulhu-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmulhu.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmv-copy.mir
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
vmv.s.x-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmv.s.x-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmv.v.v-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmv.v.v-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmv.v.x-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmv.v.x-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmv.x.s-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmv.x.s-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmxnor.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vmxor.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vnclip.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vnclipu.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vnmsac-vp.ll
[RISCV] Add isel patterns for vmacc, vnmsac.
2022-10-12 09:19:01 +08:00
vnmsac.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vnmsub-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vnmsub.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vnsra-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vnsra-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vnsra-sdnode.ll
[DAG] Teach isConstOrConstSplat about SPLAT_VECTORs
2022-12-08 11:53:25 +00:00
vnsrl-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vnsrl-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vnsrl-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vor-sdnode.ll
[RISCV] Fold vector binary operatrion into select with identity constant.
2022-12-06 11:19:31 +08:00
vor-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vor.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vpgather-sdnode.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vpload.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vpmerge-sdnode.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
vpscatter-sdnode.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
vpstore.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
vredand-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vredand-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vredmax-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vredmax-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vredmaxu-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vredmaxu-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vredmin-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vredmin-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vredminu-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vredminu-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vredor-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vredor-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vredsum-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vredsum-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vreductions-fp-sdnode.ll
[RISCV] Reuse VL (if non-zero) when building single element vector for start of reduction chain
2022-12-13 12:16:26 -08:00
vreductions-fp-vp.ll
[RISCV] Allow fractional LMUL for reduction start value
2022-12-12 09:08:21 -08:00
vreductions-int-vp.ll
[RISCV][InsertVSETVLI] Mutate prior vsetvli AVL if doing so allows us to remove a toggle
2022-12-15 07:32:28 -08:00
vreductions-int.ll
[RISCV][InsertVSETVLI] Mutate prior vsetvli AVL if doing so allows us to remove a toggle
2022-12-15 07:32:28 -08:00
vreductions-mask-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vreductions-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vredxor-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vredxor-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vrem-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vrem-vp.ll
[SDAG] Allow scalable vectors in ComputeNumSignBits (try 2)
2022-11-29 08:25:05 -08:00
vrem.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vremu-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vremu-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vremu.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vrgather-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vrgather-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vrgatherei16-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vrgatherei16-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vrgatherei16-subreg-liveness.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vrsub-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vrsub-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vrsub.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsadd-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsadd-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsadd-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsaddu-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsaddu-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsaddu-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsbc.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vscale-power-of-two.ll
[RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibility.
2022-12-06 10:31:17 -08:00
vse.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vselect-fp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
vselect-int.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vselect-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vselect-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
vsetvl-ext.ll
…
vsetvli-insert-crossbb.ll
[RISCV] Add ANDI to getRegAllocationHints.
2022-11-30 20:59:02 -08:00
vsetvli-insert-crossbb.mir
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsetvli-insert.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsetvli-insert.mir
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsetvli-regression.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsext-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsext-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vsext.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vshl-sdnode.ll
[RISCV] Fold vector binary operatrion into select with identity constant.
2022-12-06 11:19:31 +08:00
vshl-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vsitofp-vp-mask.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
vsitofp-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
vslide1down-constant-vl-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vslide1down-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vslide1down-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vslide1up-constant-vl-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vslide1up-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vslide1up-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vslidedown-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vslidedown-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vslideup-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vslideup-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsll-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsll-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsm.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsmul-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsmul-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsoxei-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsoxei.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsoxseg-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsoxseg-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsplats-fp.ll
[RISCV] Don't use zero-stride vector load if there's no optimized u-arch
2022-11-14 13:51:30 +08:00
vsplats-i1.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsplats-i64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsra-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsra-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsra-sdnode.ll
[RISCV] Fold vector binary operatrion into select with identity constant.
2022-12-06 11:19:31 +08:00
vsra-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vsrl-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsrl-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsrl-sdnode.ll
[RISCV] Fold vector binary operatrion into select with identity constant.
2022-12-06 11:19:31 +08:00
vsrl-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vsse.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsseg-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsseg-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssra-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssra-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssrl-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssrl-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssseg-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssseg-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssub-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssub-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssub-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssubu-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssubu-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vssubu-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsub-sdnode.ll
[RISCV] Fold vector binary operatrion into select with identity constant.
2022-12-06 11:19:31 +08:00
vsub-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vsub.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsuxei-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsuxei.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsuxseg-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vsuxseg-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vtrunc-vp-mask.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vtrunc-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
vtruncs-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vuitofp-vp-mask.ll
[RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF.
2022-10-06 15:44:39 -07:00
vuitofp-vp.ll
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
vwadd-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwadd-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwadd-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwadd.w-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwadd.w-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwaddu-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwaddu-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwaddu.w-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwaddu.w-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmacc-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmacc-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmacc-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmaccsu-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmaccsu-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmaccu-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmaccu-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmaccus-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmaccus-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmul-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmul-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmul-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmulsu-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
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vwmulsu-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmulu-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwmulu-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwredsum-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwredsum-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwredsumu-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwredsumu-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwsub-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwsub-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwsub-sdnode.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwsub.w-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwsub.w-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwsubu-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwsubu-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwsubu.w-rv32.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vwsubu.w-rv64.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
vxor-sdnode.ll
[RISCV] Fold vector binary operatrion into select with identity constant.
2022-12-06 11:19:31 +08:00
vxor-vp.ll
[RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand.
2022-10-11 16:40:16 -07:00
vxor.ll
[RISCV] Merge more rv32/rv64 vector intrinsic tests that contain the same content.
2022-10-08 18:30:40 -07:00
vzext-vp-mask.ll
[RISCV][InsertVSETVLI] Default to MA not MU
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vzext-vp.ll
[RISCV] Use branchless form for selects with 0 in either arm
2022-10-12 13:51:52 -07:00
vzext.ll
[RISCV][InsertVSETVLI] Default to MA not MU
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wrong-chain-fixed-load.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
wrong-stack-offset-for-rvv-object.mir
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
wrong-stack-slot-rv32.mir
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
wrong-stack-slot-rv64.mir
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
zve32-types.ll
[RISCV][InsertVSETVLI] Default to MA not MU
2022-10-06 07:59:39 -07:00
zvlsseg-copy.mir
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
zvlsseg-spill.mir
[RISCV] Move VSPILL/VRELOAD expansion for vector tuples to eliminateFrameIndex.
2022-12-06 15:42:00 -08:00
zvlsseg-zero-vl.ll
[RISCV][InsertVSETVLI] Default to MA not MU
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