b9f67d44ba
Currently the device kernels all have weak linkage to prevent linkage errors on multiple defintions. However, this prevents some optimizations from adequately analyzing them because of the nature of weak linkage. This patch replaces the weak linkage with weak_odr linkage so we can statically assert that multiple declarations of the same kernel will have the same definition. Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D122443
235 lines
8.6 KiB
C++
235 lines
8.6 KiB
C++
// Test target codegen - host bc file has to be created first.
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -debug-info-kind=limited -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -debug-info-kind=limited -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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template <typename tx, typename ty>
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struct TT {
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tx X;
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ty Y;
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};
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// TCHECK-DAG: [[TTII:%.+]] = type { i32, i32 }
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// TCHECK-DAG: [[TTIC:%.+]] = type { i8, i8 }
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// TCHECK-DAG: [[TT:%.+]] = type { i64, i8 }
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// TCHECK-DAG: [[S1:%.+]] = type { double }
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int foo(int n, double *ptr) {
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int a = 0;
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short aa = 0;
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float b[10];
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double c[5][10];
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TT<long long, char> d;
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const TT<int, int> e = {n, n};
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#pragma omp target firstprivate(a, e) map(tofrom \
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: b)
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{
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b[a] = a;
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b[a] += e.X;
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}
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// TCHECK: define {{.*}}void @__omp_offloading_{{.+}}([10 x float] addrspace(1)* noalias noundef [[B_IN:%.+]], i{{[0-9]+}} noundef [[A_IN:%.+]], [[TTII]]* noalias noundef [[E_IN:%.+]])
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// TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}},
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// TCHECK-NOT: alloca [[TTII]],
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// TCHECK: alloca i{{[0-9]+}},
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// TCHECK: store i{{[0-9]+}} [[A_IN]], i{{[0-9]+}}* [[A_ADDR]],
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// TCHECK: ret void
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#pragma omp target firstprivate(aa, b, c, d)
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{
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aa += 1;
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b[2] = 1.0;
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c[1][2] = 1.0;
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d.X = 1;
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d.Y = 1;
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}
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// make sure that firstprivate variables are generated in all cases and that we use those instances for operations inside the
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// target region
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// TCHECK: define {{.*}}void @__omp_offloading_{{.+}}(i{{[0-9]+}}{{.*}} [[A2_IN:%.+]], [10 x float]*{{.*}} [[B_IN:%.+]], [5 x [10 x double]]*{{.*}} [[C_IN:%.+]], [[TT]]*{{.*}} [[D_IN:%.+]])
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// TCHECK: [[A2_ADDR:%.+]] = alloca i{{[0-9]+}},
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// TCHECK: [[B_ADDR:%.+]] = alloca [10 x float]*,
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// TCHECK: [[C_ADDR:%.+]] = alloca [5 x [10 x double]]*,
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// TCHECK: [[D_ADDR:%.+]] = alloca [[TT]]*,
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// TCHECK-NOT: alloca i{{[0-9]+}},
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// TCHECK: [[B_PRIV:%.+]] = alloca [10 x float],
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// TCHECK: [[C_PRIV:%.+]] = alloca [5 x [10 x double]],
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// TCHECK: [[D_PRIV:%.+]] = alloca [[TT]],
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// TCHECK: store i{{[0-9]+}} [[A2_IN]], i{{[0-9]+}}* [[A2_ADDR]],
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// TCHECK: store [10 x float]* [[B_IN]], [10 x float]** [[B_ADDR]],
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// TCHECK: store [5 x [10 x double]]* [[C_IN]], [5 x [10 x double]]** [[C_ADDR]],
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// TCHECK: store [[TT]]* [[D_IN]], [[TT]]** [[D_ADDR]],
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// TCHECK: [[B_ADDR_REF:%.+]] = load [10 x float]*, [10 x float]** [[B_ADDR]],
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// TCHECK: [[B_ADDR_REF:%.+]] = load [10 x float]*, [10 x float]** %
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// TCHECK: [[C_ADDR_REF:%.+]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]],
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// TCHECK: [[C_ADDR_REF:%.+]] = load [5 x [10 x double]]*, [5 x [10 x double]]** %
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// TCHECK: [[D_ADDR_REF:%.+]] = load [[TT]]*, [[TT]]** [[D_ADDR]],
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// TCHECK: [[D_ADDR_REF:%.+]] = load [[TT]]*, [[TT]]** %
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// firstprivate(aa): a_priv = a_in
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// firstprivate(b): memcpy(b_priv,b_in)
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// TCHECK: [[B_PRIV_BCAST:%.+]] = bitcast [10 x float]* [[B_PRIV]] to i8*
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// TCHECK: [[B_ADDR_REF_BCAST:%.+]] = bitcast [10 x float]* [[B_ADDR_REF]] to i8*
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// TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[B_PRIV_BCAST]], i8* align {{[0-9]+}} [[B_ADDR_REF_BCAST]], {{.+}})
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// firstprivate(c)
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// TCHECK: [[C_PRIV_BCAST:%.+]] = bitcast [5 x [10 x double]]* [[C_PRIV]] to i8*
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// TCHECK: [[C_IN_BCAST:%.+]] = bitcast [5 x [10 x double]]* [[C_ADDR_REF]] to i8*
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// TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[C_PRIV_BCAST]], i8* align {{[0-9]+}} [[C_IN_BCAST]],{{.+}})
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// firstprivate(d)
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// TCHECK: [[D_PRIV_BCAST:%.+]] = bitcast [[TT]]* [[D_PRIV]] to i8*
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// TCHECK: [[D_IN_BCAST:%.+]] = bitcast [[TT]]* [[D_ADDR_REF]] to i8*
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// TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[D_PRIV_BCAST]], i8* align {{[0-9]+}} [[D_IN_BCAST]],{{.+}})
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// TCHECK: load i16, i16* [[A2_ADDR]],
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#pragma omp target firstprivate(ptr)
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{
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ptr[0]++;
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}
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// TCHECK: define weak_odr void @__omp_offloading_{{.+}}(double* noundef [[PTR_IN:%.+]])
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// TCHECK: [[PTR_ADDR:%.+]] = alloca double*,
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// TCHECK-NOT: alloca double*,
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// TCHECK: store double* [[PTR_IN]], double** [[PTR_ADDR]],
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// TCHECK: [[PTR_IN_REF:%.+]] = load double*, double** [[PTR_ADDR]],
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// TCHECK-NOT: store double* [[PTR_IN_REF]], double** {{%.+}},
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return a;
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}
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template <typename tx>
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tx ftemplate(int n) {
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tx a = 0;
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tx b[10];
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#pragma omp target firstprivate(a, b)
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{
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a += 1;
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b[2] += 1;
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}
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return a;
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}
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static int fstatic(int n) {
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int a = 0;
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char aaa = 0;
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int b[10];
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#pragma omp target firstprivate(a, aaa, b)
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{
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a += 1;
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aaa += 1;
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b[2] += 1;
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}
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return a;
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}
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template <typename tx>
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void fconst(const tx t) {
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#pragma omp target firstprivate(t)
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{ }
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}
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// TCHECK: define {{.*}}void @__omp_offloading_{{.+}}(i{{[0-9]+}}{{.*}} [[A_IN:%.+]], i{{[0-9]+}}{{.*}} [[A3_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} [[B_IN:%.+]])
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// TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}},
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// TCHECK: [[A3_ADDR:%.+]] = alloca i{{[0-9]+}},
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// TCHECK: [[B_ADDR:%.+]] = alloca [10 x i{{[0-9]+}}]*,
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// TCHECK-NOT: alloca i{{[0-9]+}},
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// TCHECK: [[B_PRIV:%.+]] = alloca [10 x i{{[0-9]+}}],
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// TCHECK: store i{{[0-9]+}} [[A_IN]], i{{[0-9]+}}* [[A_ADDR]],
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// TCHECK: store i{{[0-9]+}} [[A3_IN]], i{{[0-9]+}}* [[A3_ADDR]],
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// TCHECK: store [10 x i{{[0-9]+}}]* [[B_IN]], [10 x i{{[0-9]+}}]** [[B_ADDR]],
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// TCHECK: [[B_ADDR_REF:%.+]] = load [10 x i{{[0-9]+}}]*, [10 x i{{[0-9]+}}]** [[B_ADDR]],
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// TCHECK: [[B_ADDR_REF:%.+]] = load [10 x i{{[0-9]+}}]*, [10 x i{{[0-9]+}}]** %
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// firstprivate(a): a_priv = a_in
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// firstprivate(aaa)
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// TCHECK-NOT: store i{{[0-9]+}} %{{.+}}, i{{[0-9]+}}*
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// firstprivate(b)
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// TCHECK: [[B_PRIV_BCAST:%.+]] = bitcast [10 x i{{[0-9]+}}]* [[B_PRIV]] to i8*
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// TCHECK: [[B_IN_BCAST:%.+]] = bitcast [10 x i{{[0-9]+}}]* [[B_ADDR_REF]] to i8*
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// TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[B_PRIV_BCAST]], i8* align {{[0-9]+}} [[B_IN_BCAST]],{{.+}})
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// TCHECK: ret void
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struct S1 {
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double a;
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int r1(int n) {
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int b = n + 1;
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#pragma omp target firstprivate(b)
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{
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this->a = (double)b + 1.5;
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}
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return (int)b;
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}
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// TCHECK: define internal void @__omp_offloading_{{.+}}([[S1]]* noundef [[TH:%.+]], i{{[0-9]+}} noundef [[B_IN:%.+]])
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// TCHECK: [[TH_ADDR:%.+]] = alloca [[S1]]*,
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// TCHECK: [[B_ADDR:%.+]] = alloca i{{[0-9]+}},
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// TCHECK-NOT: alloca i{{[0-9]+}},
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// TCHECK: store [[S1]]* [[TH]], [[S1]]** [[TH_ADDR]],
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// TCHECK: store i{{[0-9]+}} [[B_IN]], i{{[0-9]+}}* [[B_ADDR]],
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// TCHECK: [[TH_ADDR_REF:%.+]] = load [[S1]]*, [[S1]]** [[TH_ADDR]],
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// TCHECK-64: [[B_ADDR_CONV:%.+]] = bitcast i{{[0-9]+}}* [[B_ADDR]] to i{{[0-9]+}}*
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// firstprivate(b)
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// TCHECK-NOT: store i{{[0-9]+}} %{{.+}}, i{{[0-9]+}}*
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// TCHECK: ret void
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};
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int bar(int n, double *ptr) {
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int a = 0;
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a += foo(n, ptr);
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S1 S;
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a += S.r1(n);
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a += fstatic(n);
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a += ftemplate<int>(n);
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fconst(TT<int, int>{0, 0});
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fconst(TT<char, char>{0, 0});
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return a;
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}
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// template
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// TCHECK: define internal void @__omp_offloading_{{.+}}(i{{[0-9]+}} noundef [[A_IN:%.+]], [10 x i{{[0-9]+}}]*{{.+}} noundef [[B_IN:%.+]])
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// TCHECK: [[A_ADDR:%.+]] = alloca i{{[0-9]+}},
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// TCHECK: [[B_ADDR:%.+]] = alloca [10 x i{{[0-9]+}}]*,
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// TCHECK-NOT: alloca i{{[0-9]+}},
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// TCHECK: [[B_PRIV:%.+]] = alloca [10 x i{{[0-9]+}}],
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// TCHECK: store i{{[0-9]+}} [[A_IN]], i{{[0-9]+}}* [[A_ADDR]],
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// TCHECK: store [10 x i{{[0-9]+}}]* [[B_IN]], [10 x i{{[0-9]+}}]** [[B_ADDR]],
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// TCHECK: [[B_ADDR_REF:%.+]] = load [10 x i{{[0-9]+}}]*, [10 x i{{[0-9]+}}]** [[B_ADDR]],
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// TCHECK: [[B_ADDR_REF:%.+]] = load [10 x i{{[0-9]+}}]*, [10 x i{{[0-9]+}}]** %
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// firstprivate(a)
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// TCHECK-NOT: store i{{[0-9]+}} %{{.+}}, i{{[0-9]+}}*
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// firstprivate(b)
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// TCHECK: [[B_PRIV_BCAST:%.+]] = bitcast [10 x i{{[0-9]+}}]* [[B_PRIV]] to i8*
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// TCHECK: [[B_IN_BCAST:%.+]] = bitcast [10 x i{{[0-9]+}}]* [[B_ADDR_REF]] to i8*
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// TCHECK: call void @llvm.memcpy.{{.+}}(i8* align {{[0-9]+}} [[B_PRIV_BCAST]], i8* align {{[0-9]+}} [[B_IN_BCAST]],{{.+}})
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// TCHECK: ret void
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#endif
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