llvm-project/llvm/docs/AMDGPU/gfx8_soffset_2.rst
Dmitry Preobrazhensky 8ea3e9d9a2 [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- Added f16 omod modifier (bug 51386).
- Corrected names of data types (bug 48638).
- Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231).
- Corrected description of integer operands (bug 51130).
- Corrected description of 8-bit DS offsets (bug 51536).
- Improved PERMLANE op_sel description.
- Corrected *SAD* opcode types.
2021-08-27 17:23:20 +03:00

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.. _amdgpu_synid_gfx8_soffset_2:
soffset
=======
An unsigned byte offset added to the base address to get memory address.
*Size:* 1 dword.
*Operands:* :ref:`m0<amdgpu_synid_m0>`, :ref:`uimm20<amdgpu_synid_uimm20>`