8ea3e9d9a2
Summary of changes: - Added f16 omod modifier (bug 51386). - Corrected names of data types (bug 48638). - Enabled a16 with most GFX10 MIMG opcodes (see https://reviews.llvm.org/D102231). - Corrected description of integer operands (bug 51130). - Corrected description of 8-bit DS offsets (bug 51536). - Improved PERMLANE op_sel description. - Corrected *SAD* opcode types.
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* *
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* Automatically generated file, do not edit! *
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.. _amdgpu_synid_gfx8_vdata_6:
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vdata
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=====
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Image data to store by an *image_store* instruction.
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*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>` and :ref:`d16<amdgpu_synid_d16>`:
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* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
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* :ref:`d16<amdgpu_synid_d16>` has different meaning for GFX8.0 and GFX8.1:
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* For GFX8.0 this modifier does not affect size of data elements in registers. Data in registers are stored in low 16 bits, high 16 bits are unused. There is no packing.
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* Starting from GFX8.1 this modifier specifies that data elements in registers are packed; each value occupies 16 bits.
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*Operands:* :ref:`v<amdgpu_synid_v>`
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