ed98c1b376
Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup Differential Revision: https://reviews.llvm.org/D121332
491 lines
18 KiB
C++
491 lines
18 KiB
C++
//=== lib/CodeGen/GlobalISel/AArch64PreLegalizerCombiner.cpp --------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass does combining of machine instructions at the generic MI level,
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// before the legalizer.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64GlobalISelUtils.h"
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#include "AArch64TargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
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#include "llvm/CodeGen/GlobalISel/Combiner.h"
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "aarch64-prelegalizer-combiner"
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using namespace llvm;
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using namespace MIPatternMatch;
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/// Return true if a G_FCONSTANT instruction is known to be better-represented
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/// as a G_CONSTANT.
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static bool matchFConstantToConstant(MachineInstr &MI,
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MachineRegisterInfo &MRI) {
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assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT);
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Register DstReg = MI.getOperand(0).getReg();
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const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
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if (DstSize != 32 && DstSize != 64)
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return false;
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// When we're storing a value, it doesn't matter what register bank it's on.
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// Since not all floating point constants can be materialized using a fmov,
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// it makes more sense to just use a GPR.
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return all_of(MRI.use_nodbg_instructions(DstReg),
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[](const MachineInstr &Use) { return Use.mayStore(); });
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}
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/// Change a G_FCONSTANT into a G_CONSTANT.
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static void applyFConstantToConstant(MachineInstr &MI) {
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assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT);
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MachineIRBuilder MIB(MI);
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const APFloat &ImmValAPF = MI.getOperand(1).getFPImm()->getValueAPF();
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MIB.buildConstant(MI.getOperand(0).getReg(), ImmValAPF.bitcastToAPInt());
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MI.eraseFromParent();
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}
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/// Try to match a G_ICMP of a G_TRUNC with zero, in which the truncated bits
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/// are sign bits. In this case, we can transform the G_ICMP to directly compare
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/// the wide value with a zero.
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static bool matchICmpRedundantTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
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GISelKnownBits *KB, Register &MatchInfo) {
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assert(MI.getOpcode() == TargetOpcode::G_ICMP && KB);
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auto Pred = (CmpInst::Predicate)MI.getOperand(1).getPredicate();
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if (!ICmpInst::isEquality(Pred))
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return false;
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Register LHS = MI.getOperand(2).getReg();
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LLT LHSTy = MRI.getType(LHS);
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if (!LHSTy.isScalar())
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return false;
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Register RHS = MI.getOperand(3).getReg();
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Register WideReg;
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if (!mi_match(LHS, MRI, m_GTrunc(m_Reg(WideReg))) ||
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!mi_match(RHS, MRI, m_SpecificICst(0)))
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return false;
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LLT WideTy = MRI.getType(WideReg);
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if (KB->computeNumSignBits(WideReg) <=
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WideTy.getSizeInBits() - LHSTy.getSizeInBits())
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return false;
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MatchInfo = WideReg;
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return true;
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}
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static bool applyICmpRedundantTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &Builder,
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GISelChangeObserver &Observer,
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Register &WideReg) {
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assert(MI.getOpcode() == TargetOpcode::G_ICMP);
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LLT WideTy = MRI.getType(WideReg);
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// We're going to directly use the wide register as the LHS, and then use an
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// equivalent size zero for RHS.
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Builder.setInstrAndDebugLoc(MI);
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auto WideZero = Builder.buildConstant(WideTy, 0);
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Observer.changingInstr(MI);
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MI.getOperand(2).setReg(WideReg);
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MI.getOperand(3).setReg(WideZero.getReg(0));
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Observer.changedInstr(MI);
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return true;
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}
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/// \returns true if it is possible to fold a constant into a G_GLOBAL_VALUE.
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///
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/// e.g.
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///
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/// %g = G_GLOBAL_VALUE @x -> %g = G_GLOBAL_VALUE @x + cst
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static bool matchFoldGlobalOffset(MachineInstr &MI, MachineRegisterInfo &MRI,
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std::pair<uint64_t, uint64_t> &MatchInfo) {
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assert(MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE);
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MachineFunction &MF = *MI.getMF();
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auto &GlobalOp = MI.getOperand(1);
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auto *GV = GlobalOp.getGlobal();
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if (GV->isThreadLocal())
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return false;
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// Don't allow anything that could represent offsets etc.
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if (MF.getSubtarget<AArch64Subtarget>().ClassifyGlobalReference(
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GV, MF.getTarget()) != AArch64II::MO_NO_FLAG)
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return false;
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// Look for a G_GLOBAL_VALUE only used by G_PTR_ADDs against constants:
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//
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// %g = G_GLOBAL_VALUE @x
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// %ptr1 = G_PTR_ADD %g, cst1
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// %ptr2 = G_PTR_ADD %g, cst2
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// ...
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// %ptrN = G_PTR_ADD %g, cstN
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//
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// Identify the *smallest* constant. We want to be able to form this:
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//
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// %offset_g = G_GLOBAL_VALUE @x + min_cst
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// %g = G_PTR_ADD %offset_g, -min_cst
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// %ptr1 = G_PTR_ADD %g, cst1
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// ...
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Register Dst = MI.getOperand(0).getReg();
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uint64_t MinOffset = -1ull;
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for (auto &UseInstr : MRI.use_nodbg_instructions(Dst)) {
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if (UseInstr.getOpcode() != TargetOpcode::G_PTR_ADD)
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return false;
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auto Cst = getIConstantVRegValWithLookThrough(
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UseInstr.getOperand(2).getReg(), MRI);
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if (!Cst)
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return false;
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MinOffset = std::min(MinOffset, Cst->Value.getZExtValue());
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}
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// Require that the new offset is larger than the existing one to avoid
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// infinite loops.
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uint64_t CurrOffset = GlobalOp.getOffset();
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uint64_t NewOffset = MinOffset + CurrOffset;
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if (NewOffset <= CurrOffset)
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return false;
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// Check whether folding this offset is legal. It must not go out of bounds of
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// the referenced object to avoid violating the code model, and must be
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// smaller than 2^21 because this is the largest offset expressible in all
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// object formats.
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//
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// This check also prevents us from folding negative offsets, which will end
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// up being treated in the same way as large positive ones. They could also
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// cause code model violations, and aren't really common enough to matter.
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if (NewOffset >= (1 << 21))
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return false;
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Type *T = GV->getValueType();
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if (!T->isSized() ||
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NewOffset > GV->getParent()->getDataLayout().getTypeAllocSize(T))
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return false;
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MatchInfo = std::make_pair(NewOffset, MinOffset);
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return true;
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}
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static bool applyFoldGlobalOffset(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B,
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GISelChangeObserver &Observer,
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std::pair<uint64_t, uint64_t> &MatchInfo) {
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// Change:
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//
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// %g = G_GLOBAL_VALUE @x
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// %ptr1 = G_PTR_ADD %g, cst1
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// %ptr2 = G_PTR_ADD %g, cst2
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// ...
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// %ptrN = G_PTR_ADD %g, cstN
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//
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// To:
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//
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// %offset_g = G_GLOBAL_VALUE @x + min_cst
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// %g = G_PTR_ADD %offset_g, -min_cst
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// %ptr1 = G_PTR_ADD %g, cst1
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// ...
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// %ptrN = G_PTR_ADD %g, cstN
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//
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// Then, the original G_PTR_ADDs should be folded later on so that they look
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// like this:
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//
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// %ptrN = G_PTR_ADD %offset_g, cstN - min_cst
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uint64_t Offset, MinOffset;
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std::tie(Offset, MinOffset) = MatchInfo;
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B.setInstrAndDebugLoc(MI);
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Observer.changingInstr(MI);
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auto &GlobalOp = MI.getOperand(1);
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auto *GV = GlobalOp.getGlobal();
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GlobalOp.ChangeToGA(GV, Offset, GlobalOp.getTargetFlags());
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Register Dst = MI.getOperand(0).getReg();
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Register NewGVDst = MRI.cloneVirtualRegister(Dst);
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MI.getOperand(0).setReg(NewGVDst);
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Observer.changedInstr(MI);
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B.buildPtrAdd(
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Dst, NewGVDst,
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B.buildConstant(LLT::scalar(64), -static_cast<int64_t>(MinOffset)));
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return true;
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}
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static bool tryToSimplifyUADDO(MachineInstr &MI, MachineIRBuilder &B,
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CombinerHelper &Helper,
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GISelChangeObserver &Observer) {
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// Try simplify G_UADDO with 8 or 16 bit operands to wide G_ADD and TBNZ if
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// result is only used in the no-overflow case. It is restricted to cases
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// where we know that the high-bits of the operands are 0. If there's an
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// overflow, then the the 9th or 17th bit must be set, which can be checked
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// using TBNZ.
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//
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// Change (for UADDOs on 8 and 16 bits):
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//
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// %z0 = G_ASSERT_ZEXT _
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// %op0 = G_TRUNC %z0
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// %z1 = G_ASSERT_ZEXT _
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// %op1 = G_TRUNC %z1
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// %val, %cond = G_UADDO %op0, %op1
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// G_BRCOND %cond, %error.bb
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//
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// error.bb:
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// (no successors and no uses of %val)
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//
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// To:
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//
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// %z0 = G_ASSERT_ZEXT _
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// %z1 = G_ASSERT_ZEXT _
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// %add = G_ADD %z0, %z1
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// %val = G_TRUNC %add
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// %bit = G_AND %add, 1 << scalar-size-in-bits(%op1)
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// %cond = G_ICMP NE, %bit, 0
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// G_BRCOND %cond, %error.bb
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auto &MRI = *B.getMRI();
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MachineOperand *DefOp0 = MRI.getOneDef(MI.getOperand(2).getReg());
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MachineOperand *DefOp1 = MRI.getOneDef(MI.getOperand(3).getReg());
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Register Op0Wide;
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Register Op1Wide;
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if (!mi_match(DefOp0->getParent(), MRI, m_GTrunc(m_Reg(Op0Wide))) ||
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!mi_match(DefOp1->getParent(), MRI, m_GTrunc(m_Reg(Op1Wide))))
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return false;
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LLT WideTy0 = MRI.getType(Op0Wide);
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LLT WideTy1 = MRI.getType(Op1Wide);
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Register ResVal = MI.getOperand(0).getReg();
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LLT OpTy = MRI.getType(ResVal);
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MachineInstr *Op0WideDef = MRI.getVRegDef(Op0Wide);
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MachineInstr *Op1WideDef = MRI.getVRegDef(Op1Wide);
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unsigned OpTySize = OpTy.getScalarSizeInBits();
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// First check that the G_TRUNC feeding the G_UADDO are no-ops, because the
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// inputs have been zero-extended.
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if (Op0WideDef->getOpcode() != TargetOpcode::G_ASSERT_ZEXT ||
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Op1WideDef->getOpcode() != TargetOpcode::G_ASSERT_ZEXT ||
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OpTySize != Op0WideDef->getOperand(2).getImm() ||
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OpTySize != Op1WideDef->getOperand(2).getImm())
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return false;
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// Only scalar UADDO with either 8 or 16 bit operands are handled.
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if (!WideTy0.isScalar() || !WideTy1.isScalar() || WideTy0 != WideTy1 ||
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OpTySize >= WideTy0.getScalarSizeInBits() ||
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(OpTySize != 8 && OpTySize != 16))
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return false;
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// The overflow-status result must be used by a branch only.
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Register ResStatus = MI.getOperand(1).getReg();
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if (!MRI.hasOneNonDBGUse(ResStatus))
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return false;
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MachineInstr *CondUser = &*MRI.use_instr_nodbg_begin(ResStatus);
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if (CondUser->getOpcode() != TargetOpcode::G_BRCOND)
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return false;
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// Make sure the computed result is only used in the no-overflow blocks.
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MachineBasicBlock *CurrentMBB = MI.getParent();
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MachineBasicBlock *FailMBB = CondUser->getOperand(1).getMBB();
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if (!FailMBB->succ_empty() || CondUser->getParent() != CurrentMBB)
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return false;
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if (any_of(MRI.use_nodbg_instructions(ResVal),
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[&MI, FailMBB, CurrentMBB](MachineInstr &I) {
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return &MI != &I &&
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(I.getParent() == FailMBB || I.getParent() == CurrentMBB);
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}))
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return false;
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// Remove G_ADDO.
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B.setInstrAndDebugLoc(*MI.getNextNode());
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MI.eraseFromParent();
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// Emit wide add.
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Register AddDst = MRI.cloneVirtualRegister(Op0Wide);
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B.buildInstr(TargetOpcode::G_ADD, {AddDst}, {Op0Wide, Op1Wide});
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// Emit check of the 9th or 17th bit and update users (the branch). This will
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// later be folded to TBNZ.
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Register CondBit = MRI.cloneVirtualRegister(Op0Wide);
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B.buildAnd(
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CondBit, AddDst,
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B.buildConstant(LLT::scalar(32), OpTySize == 8 ? 1 << 8 : 1 << 16));
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B.buildICmp(CmpInst::ICMP_NE, ResStatus, CondBit,
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B.buildConstant(LLT::scalar(32), 0));
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// Update ZEXts users of the result value. Because all uses are in the
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// no-overflow case, we know that the top bits are 0 and we can ignore ZExts.
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B.buildZExtOrTrunc(ResVal, AddDst);
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for (MachineOperand &U : make_early_inc_range(MRI.use_operands(ResVal))) {
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Register WideReg;
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if (mi_match(U.getParent(), MRI, m_GZExt(m_Reg(WideReg)))) {
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auto OldR = U.getParent()->getOperand(0).getReg();
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Observer.erasingInstr(*U.getParent());
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U.getParent()->eraseFromParent();
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Helper.replaceRegWith(MRI, OldR, AddDst);
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}
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}
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return true;
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}
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class AArch64PreLegalizerCombinerHelperState {
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protected:
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CombinerHelper &Helper;
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public:
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AArch64PreLegalizerCombinerHelperState(CombinerHelper &Helper)
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: Helper(Helper) {}
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};
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#define AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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#include "AArch64GenPreLegalizeGICombiner.inc"
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#undef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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namespace {
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#define AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
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#include "AArch64GenPreLegalizeGICombiner.inc"
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#undef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
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class AArch64PreLegalizerCombinerInfo : public CombinerInfo {
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GISelKnownBits *KB;
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MachineDominatorTree *MDT;
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AArch64GenPreLegalizerCombinerHelperRuleConfig GeneratedRuleCfg;
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public:
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AArch64PreLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
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GISelKnownBits *KB, MachineDominatorTree *MDT)
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: CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
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/*LegalizerInfo*/ nullptr, EnableOpt, OptSize, MinSize),
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KB(KB), MDT(MDT) {
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if (!GeneratedRuleCfg.parseCommandLineOption())
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report_fatal_error("Invalid rule identifier");
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}
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virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
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MachineIRBuilder &B) const override;
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};
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bool AArch64PreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
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MachineInstr &MI,
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MachineIRBuilder &B) const {
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CombinerHelper Helper(Observer, B, KB, MDT);
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AArch64GenPreLegalizerCombinerHelper Generated(GeneratedRuleCfg, Helper);
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if (Generated.tryCombineAll(Observer, MI, B))
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return true;
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unsigned Opc = MI.getOpcode();
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switch (Opc) {
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case TargetOpcode::G_CONCAT_VECTORS:
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return Helper.tryCombineConcatVectors(MI);
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case TargetOpcode::G_SHUFFLE_VECTOR:
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return Helper.tryCombineShuffleVector(MI);
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case TargetOpcode::G_UADDO:
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return tryToSimplifyUADDO(MI, B, Helper, Observer);
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case TargetOpcode::G_MEMCPY_INLINE:
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return Helper.tryEmitMemcpyInline(MI);
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case TargetOpcode::G_MEMCPY:
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case TargetOpcode::G_MEMMOVE:
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case TargetOpcode::G_MEMSET: {
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// If we're at -O0 set a maxlen of 32 to inline, otherwise let the other
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// heuristics decide.
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unsigned MaxLen = EnableOpt ? 0 : 32;
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// Try to inline memcpy type calls if optimizations are enabled.
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if (Helper.tryCombineMemCpyFamily(MI, MaxLen))
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return true;
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if (Opc == TargetOpcode::G_MEMSET)
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return llvm::AArch64GISelUtils::tryEmitBZero(MI, B, EnableMinSize);
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return false;
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}
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}
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return false;
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}
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#define AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
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#include "AArch64GenPreLegalizeGICombiner.inc"
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#undef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
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// Pass boilerplate
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// ================
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class AArch64PreLegalizerCombiner : public MachineFunctionPass {
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public:
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static char ID;
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AArch64PreLegalizerCombiner();
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StringRef getPassName() const override { return "AArch64PreLegalizerCombiner"; }
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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};
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} // end anonymous namespace
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void AArch64PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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AU.setPreservesCFG();
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getSelectionDAGFallbackAnalysisUsage(AU);
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AU.addRequired<GISelKnownBitsAnalysis>();
|
|
AU.addPreserved<GISelKnownBitsAnalysis>();
|
|
AU.addRequired<MachineDominatorTree>();
|
|
AU.addPreserved<MachineDominatorTree>();
|
|
AU.addRequired<GISelCSEAnalysisWrapperPass>();
|
|
AU.addPreserved<GISelCSEAnalysisWrapperPass>();
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
}
|
|
|
|
AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner()
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|
: MachineFunctionPass(ID) {
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|
initializeAArch64PreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
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|
}
|
|
|
|
bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
|
|
if (MF.getProperties().hasProperty(
|
|
MachineFunctionProperties::Property::FailedISel))
|
|
return false;
|
|
auto &TPC = getAnalysis<TargetPassConfig>();
|
|
|
|
// Enable CSE.
|
|
GISelCSEAnalysisWrapper &Wrapper =
|
|
getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
|
|
auto *CSEInfo = &Wrapper.get(TPC.getCSEConfig());
|
|
|
|
const Function &F = MF.getFunction();
|
|
bool EnableOpt =
|
|
MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
|
|
GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
|
|
MachineDominatorTree *MDT = &getAnalysis<MachineDominatorTree>();
|
|
AArch64PreLegalizerCombinerInfo PCInfo(EnableOpt, F.hasOptSize(),
|
|
F.hasMinSize(), KB, MDT);
|
|
Combiner C(PCInfo, &TPC);
|
|
return C.combineMachineInstrs(MF, CSEInfo);
|
|
}
|
|
|
|
char AArch64PreLegalizerCombiner::ID = 0;
|
|
INITIALIZE_PASS_BEGIN(AArch64PreLegalizerCombiner, DEBUG_TYPE,
|
|
"Combine AArch64 machine instrs before legalization",
|
|
false, false)
|
|
INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
|
|
INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
|
|
INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
|
|
INITIALIZE_PASS_END(AArch64PreLegalizerCombiner, DEBUG_TYPE,
|
|
"Combine AArch64 machine instrs before legalization", false,
|
|
false)
|
|
|
|
|
|
namespace llvm {
|
|
FunctionPass *createAArch64PreLegalizerCombiner() {
|
|
return new AArch64PreLegalizerCombiner();
|
|
}
|
|
} // end namespace llvm
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