3347f77b80
This patch adds basic support to AsmParser which can handle basic instructions with register or immediate operands. With the addition of the parser, now it's possible to test instructions encoding with `llvm-mc`. Disassembler will be added later and then we can do `round-trip` test. Reviewed By: xen0n, MaskRay, myhsu Differential Revision: https://reviews.llvm.org/D120476
114 lines
4.0 KiB
C++
114 lines
4.0 KiB
C++
//===-- LoongArchMCTargetDesc.cpp - LoongArch Target Descriptions ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides LoongArch specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#include "LoongArchMCTargetDesc.h"
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#include "LoongArchBaseInfo.h"
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#include "LoongArchInstPrinter.h"
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#include "LoongArchMCAsmInfo.h"
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#include "TargetInfo/LoongArchTargetInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCDwarf.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Compiler.h"
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#define GET_INSTRINFO_MC_DESC
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#include "LoongArchGenInstrInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "LoongArchGenRegisterInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "LoongArchGenSubtargetInfo.inc"
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using namespace llvm;
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static MCRegisterInfo *createLoongArchMCRegisterInfo(const Triple &TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitLoongArchMCRegisterInfo(X, LoongArch::R1);
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return X;
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}
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static MCInstrInfo *createLoongArchMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitLoongArchMCInstrInfo(X);
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return X;
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}
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static MCSubtargetInfo *
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createLoongArchMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
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if (CPU.empty())
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CPU = TT.isArch64Bit() ? "la464" : "generic-la32";
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return createLoongArchMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
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}
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static MCAsmInfo *createLoongArchMCAsmInfo(const MCRegisterInfo &MRI,
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const Triple &TT,
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const MCTargetOptions &Options) {
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MCAsmInfo *MAI = new LoongArchMCAsmInfo(TT);
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MCRegister SP = MRI.getDwarfRegNum(LoongArch::R2, true);
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MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0);
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MAI->addInitialFrameState(Inst);
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return MAI;
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}
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static MCInstPrinter *createLoongArchMCInstPrinter(const Triple &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI) {
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return new LoongArchInstPrinter(MAI, MII, MRI);
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}
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namespace {
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class LoongArchMCInstrAnalysis : public MCInstrAnalysis {
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public:
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explicit LoongArchMCInstrAnalysis(const MCInstrInfo *Info)
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: MCInstrAnalysis(Info) {}
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bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
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uint64_t &Target) const override {
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unsigned NumOps = Inst.getNumOperands();
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if (isBranch(Inst) || Inst.getOpcode() == LoongArch::BL) {
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Target = Addr + Inst.getOperand(NumOps - 1).getImm();
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return true;
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}
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return false;
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}
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};
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} // end anonymous namespace
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static MCInstrAnalysis *createLoongArchInstrAnalysis(const MCInstrInfo *Info) {
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return new LoongArchMCInstrAnalysis(Info);
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchTargetMC() {
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for (Target *T : {&getTheLoongArch32Target(), &getTheLoongArch64Target()}) {
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TargetRegistry::RegisterMCRegInfo(*T, createLoongArchMCRegisterInfo);
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TargetRegistry::RegisterMCInstrInfo(*T, createLoongArchMCInstrInfo);
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TargetRegistry::RegisterMCSubtargetInfo(*T, createLoongArchMCSubtargetInfo);
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TargetRegistry::RegisterMCAsmInfo(*T, createLoongArchMCAsmInfo);
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TargetRegistry::RegisterMCCodeEmitter(*T, createLoongArchMCCodeEmitter);
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TargetRegistry::RegisterMCAsmBackend(*T, createLoongArchAsmBackend);
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TargetRegistry::RegisterMCInstPrinter(*T, createLoongArchMCInstPrinter);
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TargetRegistry::RegisterMCInstrAnalysis(*T, createLoongArchInstrAnalysis);
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}
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}
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