572 lines
19 KiB
C++
572 lines
19 KiB
C++
//===-- M68kMCCodeEmitter.cpp - Convert M68k code emitter -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file contains defintions for M68k code emitter.
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///
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/M68kMCCodeEmitter.h"
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#include "MCTargetDesc/M68kBaseInfo.h"
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#include "MCTargetDesc/M68kFixupKinds.h"
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#include "MCTargetDesc/M68kMCTargetDesc.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/raw_ostream.h"
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#include <type_traits>
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using namespace llvm;
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#define DEBUG_TYPE "m68k-mccodeemitter"
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namespace {
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class M68kMCCodeEmitter : public MCCodeEmitter {
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M68kMCCodeEmitter(const M68kMCCodeEmitter &) = delete;
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void operator=(const M68kMCCodeEmitter &) = delete;
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const MCInstrInfo &MCII;
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MCContext &Ctx;
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void getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
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APInt &Inst, APInt &Scratch,
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const MCSubtargetInfo &STI) const;
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void getMachineOpValue(const MCInst &MI, const MCOperand &Op,
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unsigned InsertPos, APInt &Value,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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template <unsigned Size>
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void encodeRelocImm(const MCInst &MI, unsigned OpIdx, unsigned InsertPos,
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APInt &Value, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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template <unsigned Size>
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void encodePCRelImm(const MCInst &MI, unsigned OpIdx, unsigned InsertPos,
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APInt &Value, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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public:
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M68kMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
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: MCII(mcii), Ctx(ctx) {}
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~M68kMCCodeEmitter() override {}
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// TableGen'erated function
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const uint8_t *getGenInstrBeads(const MCInst &MI) const {
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return M68k::getMCInstrBeads(MI.getOpcode());
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}
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unsigned encodeBits(unsigned ThisByte, uint8_t Bead, const MCInst &MI,
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const MCInstrDesc &Desc, uint64_t &Buffer,
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unsigned Offset, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned encodeReg(unsigned ThisByte, uint8_t Bead, const MCInst &MI,
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const MCInstrDesc &Desc, uint64_t &Buffer, unsigned Offset,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned encodeImm(unsigned ThisByte, uint8_t Bead, const MCInst &MI,
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const MCInstrDesc &Desc, uint64_t &Buffer, unsigned Offset,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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};
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} // end anonymous namespace
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#include "M68kGenMCCodeEmitter.inc"
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// Select the proper unsigned integer type from a bit size.
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template <unsigned Size> struct select_uint_t {
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using type = typename std::conditional<
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Size == 8, uint8_t,
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typename std::conditional<
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Size == 16, uint16_t,
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typename std::conditional<Size == 32, uint32_t,
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uint64_t>::type>::type>::type;
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};
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// On a LE host:
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// MSB LSB MSB LSB
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// | 0x12 0x34 | 0xAB 0xCD | -> | 0xAB 0xCD | 0x12 0x34 |
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// (On a BE host nothing changes)
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template <typename value_t> static value_t swapWord(value_t Val) {
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const unsigned NumWords = sizeof(Val) / 2;
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if (NumWords <= 1)
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return Val;
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Val = support::endian::byte_swap(Val, support::big);
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value_t NewVal = 0;
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for (unsigned i = 0U; i != NumWords; ++i) {
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uint16_t Part = (Val >> (i * 16)) & 0xFFFF;
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Part = support::endian::byte_swap(Part, support::big);
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NewVal |= (Part << (i * 16));
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}
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return NewVal;
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}
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// Figure out which byte we're at in big endian mode.
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template <unsigned Size> static unsigned getBytePosition(unsigned BitPos) {
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if (Size % 16) {
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return static_cast<unsigned>(BitPos / 8 + ((BitPos & 0b1111) < 8 ? 1 : -1));
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} else {
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assert(!(BitPos & 0b1111) && "Not aligned to word boundary?");
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return BitPos / 8;
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}
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}
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// We need special handlings for relocatable & pc-relative operands that are
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// larger than a word.
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// A M68k instruction is aligned by word (16 bits). That means, 32-bit
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// (& 64-bit) immediate values are separated into hi & lo words and placed
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// at lower & higher addresses, respectively. For immediate values that can
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// be easily expressed in TG, we explicitly rotate the word ordering like
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// this:
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// ```
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// (ascend (slice "$imm", 31, 16), (slice "$imm", 15, 0))
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// ```
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// For operands that call into encoder functions, we need to use the `swapWord`
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// function to assure the correct word ordering on LE host. Note that
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// M68kMCCodeEmitter does massage _byte_ ordering of the final encoded
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// instruction but it assumes everything aligns on word boundaries. So things
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// will go wrong if we don't take care of the _word_ ordering here.
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template <unsigned Size>
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void M68kMCCodeEmitter::encodeRelocImm(const MCInst &MI, unsigned OpIdx,
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unsigned InsertPos, APInt &Value,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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using value_t = typename select_uint_t<Size>::type;
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const MCOperand &MCO = MI.getOperand(OpIdx);
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if (MCO.isImm()) {
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Value |= swapWord<value_t>(static_cast<value_t>(MCO.getImm()));
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} else if (MCO.isExpr()) {
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const MCExpr *Expr = MCO.getExpr();
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// Absolute address
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int64_t Addr;
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if (Expr->evaluateAsAbsolute(Addr)) {
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Value |= swapWord<value_t>(static_cast<value_t>(Addr));
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return;
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}
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// Relocatable address
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unsigned InsertByte = getBytePosition<Size>(InsertPos);
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Fixups.push_back(MCFixup::create(InsertByte, Expr,
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getFixupForSize(Size, /*IsPCRel=*/false),
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MI.getLoc()));
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}
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}
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template <unsigned Size>
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void M68kMCCodeEmitter::encodePCRelImm(const MCInst &MI, unsigned OpIdx,
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unsigned InsertPos, APInt &Value,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MCO = MI.getOperand(OpIdx);
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if (MCO.isImm()) {
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using value_t = typename select_uint_t<Size>::type;
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Value |= swapWord<value_t>(static_cast<value_t>(MCO.getImm()));
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} else if (MCO.isExpr()) {
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const MCExpr *Expr = MCO.getExpr();
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unsigned InsertByte = getBytePosition<Size>(InsertPos);
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// Special handlings for sizes smaller than a word.
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if (Size < 16) {
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int LabelOffset = 0;
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if (InsertPos < 16)
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// If the patch point is at the first word, PC is pointing at the
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// next word.
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LabelOffset = InsertByte - 2;
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else if (InsertByte % 2)
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// Otherwise the PC is pointing at the first byte of this word.
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// So we need to consider the offset between PC and the fixup byte.
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LabelOffset = 1;
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if (LabelOffset)
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Expr = MCBinaryExpr::createAdd(
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Expr, MCConstantExpr::create(LabelOffset, Ctx), Ctx);
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}
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Fixups.push_back(MCFixup::create(InsertByte, Expr,
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getFixupForSize(Size, /*IsPCRel=*/true),
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MI.getLoc()));
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}
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}
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void M68kMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &Op,
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unsigned InsertPos, APInt &Value,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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// Register
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if (Op.isReg()) {
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unsigned RegNum = Op.getReg();
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const auto *RI = Ctx.getRegisterInfo();
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Value |= RI->getEncodingValue(RegNum);
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// Setup the D/A bit
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if (M68kII::isAddressRegister(RegNum))
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Value |= 0b1000;
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} else if (Op.isImm()) {
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// Immediate
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Value |= static_cast<uint64_t>(Op.getImm());
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} else if (Op.isExpr()) {
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// Absolute address
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int64_t Addr;
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if (!Op.getExpr()->evaluateAsAbsolute(Addr))
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report_fatal_error("Unsupported asm expression. Only absolute address "
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"can be placed here.");
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Value |= static_cast<uint64_t>(Addr);
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} else {
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llvm_unreachable("Unsupported operand type");
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}
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}
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unsigned M68kMCCodeEmitter::encodeBits(unsigned ThisByte, uint8_t Bead,
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const MCInst &MI,
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const MCInstrDesc &Desc,
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uint64_t &Buffer, unsigned Offset,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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unsigned Num = 0;
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switch (Bead & 0xF) {
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case M68kBeads::Bits1:
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Num = 1;
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break;
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case M68kBeads::Bits2:
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Num = 2;
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break;
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case M68kBeads::Bits3:
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Num = 3;
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break;
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case M68kBeads::Bits4:
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Num = 4;
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break;
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}
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unsigned char Val = (Bead & 0xF0) >> 4;
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LLVM_DEBUG(dbgs() << "\tEncodeBits"
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<< " Num: " << Num << " Val: 0x");
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LLVM_DEBUG(dbgs().write_hex(Val) << "\n");
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Buffer |= (Val << Offset);
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return Num;
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}
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unsigned M68kMCCodeEmitter::encodeReg(unsigned ThisByte, uint8_t Bead,
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const MCInst &MI, const MCInstrDesc &Desc,
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uint64_t &Buffer, unsigned Offset,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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bool DA, Reg;
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switch (Bead & 0xF) {
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default:
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llvm_unreachable("Unrecognized Bead code for register type");
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case M68kBeads::DAReg:
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Reg = true;
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DA = true;
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break;
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case M68kBeads::DA:
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Reg = false;
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DA = true;
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break;
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case M68kBeads::DReg:
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case M68kBeads::Reg:
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Reg = true;
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DA = false;
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break;
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}
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unsigned Op = (Bead & 0x70) >> 4;
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bool Alt = (Bead & 0x80);
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LLVM_DEBUG(dbgs() << "\tEncodeReg"
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<< " Op: " << Op << ", DA: " << DA << ", Reg: " << Reg
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<< ", Alt: " << Alt << "\n");
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auto MIOpIdx = M68k::getLogicalOperandIdx(MI.getOpcode(), Op);
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bool IsPCRel = Desc.OpInfo[MIOpIdx].OperandType == MCOI::OPERAND_PCREL;
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MCOperand MCO;
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if (M68kII::hasMultiMIOperands(MI.getOpcode(), Op)) {
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if (IsPCRel) {
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assert(Alt &&
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"PCRel addresses use Alt bead register encoding by default");
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MCO = MI.getOperand(MIOpIdx + M68k::PCRelIndex);
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} else {
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MCO = MI.getOperand(MIOpIdx + (Alt ? M68k::MemIndex : M68k::MemBase));
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}
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} else {
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assert(!Alt && "You cannot use Alt register with a simple operand");
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MCO = MI.getOperand(MIOpIdx);
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}
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unsigned RegNum = MCO.getReg();
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auto RI = Ctx.getRegisterInfo();
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unsigned Written = 0;
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if (Reg) {
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uint32_t Val = RI->getEncodingValue(RegNum);
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Buffer |= (Val & 7) << Offset;
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Offset += 3;
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Written += 3;
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}
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if (DA) {
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Buffer |= (uint64_t)M68kII::isAddressRegister(RegNum) << Offset;
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Written++;
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}
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return Written;
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}
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static unsigned EmitConstant(uint64_t Val, unsigned Size, unsigned Pad,
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uint64_t &Buffer, unsigned Offset) {
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assert(Size + Offset <= 64 && isUIntN(Size, Val) && "Value does not fit");
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// Writing Value in host's endianness
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Buffer |= (Val & ((1ULL << Size) - 1)) << Offset;
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return Size + Pad;
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}
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unsigned M68kMCCodeEmitter::encodeImm(unsigned ThisByte, uint8_t Bead,
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const MCInst &MI, const MCInstrDesc &Desc,
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uint64_t &Buffer, unsigned Offset,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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unsigned ThisWord = ThisByte / 2;
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unsigned Size = 0;
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unsigned Pad = 0;
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unsigned FixOffset = 0;
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int64_t Addendum = 0;
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bool NoExpr = false;
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unsigned Type = Bead & 0xF;
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unsigned Op = (Bead & 0x70) >> 4;
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bool Alt = (Bead & 0x80);
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auto MIOpIdx = M68k::getLogicalOperandIdx(MI.getOpcode(), Op);
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bool IsPCRel = Desc.OpInfo[MIOpIdx].OperandType == MCOI::OPERAND_PCREL;
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// The PC value upon instruction reading of a short jump will point to the
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// next instruction, thus we need to compensate 2 bytes, which is the diff
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// between the patch point and the PC.
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if (IsPCRel && ThisWord == 0)
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Addendum -= 2;
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switch (Type) {
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// ??? what happens if it is not byte aligned
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// ??? is it even possible
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case M68kBeads::Disp8:
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Size = 8;
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Pad = 0;
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FixOffset = ThisByte + 1;
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Addendum += 1;
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break;
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case M68kBeads::Imm8:
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Size = 8;
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Pad = 8;
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FixOffset = ThisByte;
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break;
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case M68kBeads::Imm16:
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Size = 16;
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Pad = 0;
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FixOffset = ThisByte;
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break;
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case M68kBeads::Imm32:
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Size = 32;
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Pad = 0;
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FixOffset = ThisByte;
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break;
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case M68kBeads::Imm3:
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Size = 3;
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Pad = 0;
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NoExpr = true;
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break;
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}
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LLVM_DEBUG(dbgs() << "\tEncodeImm"
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<< " Op: " << Op << ", Size: " << Size << ", Alt: " << Alt
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<< "\n");
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MCOperand MCO;
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if (M68kII::hasMultiMIOperands(MI.getOpcode(), Op)) {
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if (IsPCRel) {
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assert(!Alt && "You cannot use ALT operand with PCRel");
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MCO = MI.getOperand(MIOpIdx + M68k::PCRelDisp);
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} else {
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MCO = MI.getOperand(MIOpIdx + (Alt ? M68k::MemOuter : M68k::MemDisp));
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}
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if (MCO.isExpr()) {
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assert(!NoExpr && "Cannot use expression here");
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const MCExpr *Expr = MCO.getExpr();
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// This only makes sense for PCRel instructions since PC points to the
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// extension word and Disp8 for example is right justified and requires
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// correction. E.g. R_68K_PC32 is calculated as S + A - P, P for Disp8
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// will be EXTENSION_WORD + 1 thus we need to have A equal to 1 to
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// compensate.
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// TODO count extension words
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if (IsPCRel && Addendum != 0) {
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Expr = MCBinaryExpr::createAdd(
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Expr, MCConstantExpr::create(Addendum, Ctx), Ctx);
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}
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Fixups.push_back(MCFixup::create(
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FixOffset, Expr, getFixupForSize(Size, IsPCRel), MI.getLoc()));
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// Write zeros
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return EmitConstant(0, Size, Pad, Buffer, Offset);
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}
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} else {
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MCO = MI.getOperand(MIOpIdx);
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if (MCO.isExpr()) {
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assert(!NoExpr && "Cannot use expression here");
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const MCExpr *Expr = MCO.getExpr();
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if (Addendum != 0) {
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Expr = MCBinaryExpr::createAdd(
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Expr, MCConstantExpr::create(Addendum, Ctx), Ctx);
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}
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Fixups.push_back(MCFixup::create(
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FixOffset, Expr, getFixupForSize(Size, IsPCRel), MI.getLoc()));
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// Write zeros
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return EmitConstant(0, Size, Pad, Buffer, Offset);
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}
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}
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int64_t I = MCO.getImm();
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// Store 8 as 0, thus making range 1-8
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if (Type == M68kBeads::Imm3 && Alt) {
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assert(I && "Cannot encode Alt Imm3 zero value");
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I %= 8;
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} else {
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assert(isIntN(Size, I));
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}
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uint64_t Imm = I;
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// 32 bit Imm requires HI16 first then LO16
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if (Size == 32) {
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Offset += EmitConstant((Imm >> 16) & 0xFFFF, 16, Pad, Buffer, Offset);
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EmitConstant(Imm & 0xFFFF, 16, Pad, Buffer, Offset);
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return Size;
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}
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return EmitConstant(Imm & ((1ULL << Size) - 1), Size, Pad, Buffer, Offset);
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}
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#include "M68kGenMCCodeBeads.inc"
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void M68kMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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unsigned Opcode = MI.getOpcode();
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const MCInstrDesc &Desc = MCII.get(Opcode);
|
|
|
|
LLVM_DEBUG(dbgs() << "EncodeInstruction: " << MCII.getName(Opcode) << "("
|
|
<< Opcode << ")\n");
|
|
|
|
// Try using the new method first.
|
|
APInt EncodedInst(16, 0U);
|
|
APInt Scratch(16, 0U);
|
|
getBinaryCodeForInstr(MI, Fixups, EncodedInst, Scratch, STI);
|
|
if (EncodedInst.getBitWidth()) {
|
|
LLVM_DEBUG(dbgs() << "Instruction " << MCII.getName(Opcode) << "(" << Opcode
|
|
<< ") is using the new code emitter\n");
|
|
ArrayRef<uint64_t> Data(EncodedInst.getRawData(),
|
|
EncodedInst.getNumWords());
|
|
int64_t InstSize = EncodedInst.getBitWidth();
|
|
for (uint64_t Word : Data) {
|
|
for (int i = 0; i < 4 && InstSize > 0; ++i, InstSize -= 16) {
|
|
support::endian::write<uint16_t>(OS, static_cast<uint16_t>(Word),
|
|
support::big);
|
|
Word >>= 16;
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
|
|
const uint8_t *Beads = getGenInstrBeads(MI);
|
|
if (!Beads || !*Beads) {
|
|
llvm_unreachable("*** Instruction does not have Beads defined");
|
|
}
|
|
|
|
uint64_t Buffer = 0;
|
|
unsigned Offset = 0;
|
|
unsigned ThisByte = 0;
|
|
|
|
for (uint8_t Bead = *Beads; Bead; Bead = *++Beads) {
|
|
// Check for control beads
|
|
if (!(Bead & 0xF)) {
|
|
switch (Bead >> 4) {
|
|
case M68kBeads::Ignore:
|
|
continue;
|
|
}
|
|
}
|
|
|
|
switch (Bead & 0xF) {
|
|
default:
|
|
llvm_unreachable("Unknown Bead code");
|
|
break;
|
|
case M68kBeads::Bits1:
|
|
case M68kBeads::Bits2:
|
|
case M68kBeads::Bits3:
|
|
case M68kBeads::Bits4:
|
|
Offset +=
|
|
encodeBits(ThisByte, Bead, MI, Desc, Buffer, Offset, Fixups, STI);
|
|
break;
|
|
case M68kBeads::DAReg:
|
|
case M68kBeads::DA:
|
|
case M68kBeads::DReg:
|
|
case M68kBeads::Reg:
|
|
Offset +=
|
|
encodeReg(ThisByte, Bead, MI, Desc, Buffer, Offset, Fixups, STI);
|
|
break;
|
|
case M68kBeads::Disp8:
|
|
case M68kBeads::Imm8:
|
|
case M68kBeads::Imm16:
|
|
case M68kBeads::Imm32:
|
|
case M68kBeads::Imm3:
|
|
Offset +=
|
|
encodeImm(ThisByte, Bead, MI, Desc, Buffer, Offset, Fixups, STI);
|
|
break;
|
|
}
|
|
|
|
// Since M68k is Big Endian we need to rotate each instruction word
|
|
while (Offset / 16) {
|
|
support::endian::write<uint16_t>(OS, Buffer, support::big);
|
|
Buffer >>= 16;
|
|
Offset -= 16;
|
|
ThisByte += 2;
|
|
}
|
|
}
|
|
|
|
assert(Offset == 0 && "M68k Instructions are % 2 bytes");
|
|
assert((ThisByte && !(ThisByte % 2)) && "M68k Instructions are % 2 bytes");
|
|
}
|
|
|
|
MCCodeEmitter *llvm::createM68kMCCodeEmitter(const MCInstrInfo &MCII,
|
|
MCContext &Ctx) {
|
|
return new M68kMCCodeEmitter(MCII, Ctx);
|
|
}
|