e63455d5e0
On some architectures such as Arm and X86 the encoding for a nop may change depending on the subtarget in operation at the time of encoding. This change replaces the per module MCSubtargetInfo retained by the targets AsmBackend in favour of passing through the local MCSubtargetInfo in operation at the time. On Arm using the architectural NOP instruction can have a performance benefit on some implementations. For Arm I've deleted the copy of the AsmBackend's MCSubtargetInfo to limit the chances of this causing problems in the future. I've not done this for other targets such as X86 as there is more frequent use of the MCSubtargetInfo and it looks to be for stable properties that we would not expect to vary per function. This change required threading STI through MCNopsFragment and MCBoundaryAlignFragment. I've attempted to take into account the in tree experimental backends. Differential Revision: https://reviews.llvm.org/D45962
78 lines
2.5 KiB
C++
78 lines
2.5 KiB
C++
//===-- MipsAsmBackend.h - Mips Asm Backend ------------------------------===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file defines the MipsAsmBackend class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
|
|
#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H
|
|
#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H
|
|
|
|
#include "MCTargetDesc/MipsFixupKinds.h"
|
|
#include "llvm/ADT/Triple.h"
|
|
#include "llvm/MC/MCAsmBackend.h"
|
|
|
|
namespace llvm {
|
|
|
|
class MCAssembler;
|
|
struct MCFixupKindInfo;
|
|
class MCRegisterInfo;
|
|
class Target;
|
|
|
|
class MipsAsmBackend : public MCAsmBackend {
|
|
Triple TheTriple;
|
|
bool IsN32;
|
|
|
|
public:
|
|
MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT,
|
|
StringRef CPU, bool N32)
|
|
: MCAsmBackend(TT.isLittleEndian() ? support::little : support::big),
|
|
TheTriple(TT), IsN32(N32) {}
|
|
|
|
std::unique_ptr<MCObjectTargetWriter>
|
|
createObjectTargetWriter() const override;
|
|
|
|
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
|
|
const MCValue &Target, MutableArrayRef<char> Data,
|
|
uint64_t Value, bool IsResolved,
|
|
const MCSubtargetInfo *STI) const override;
|
|
|
|
Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
|
|
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
|
|
|
|
unsigned getNumFixupKinds() const override {
|
|
return Mips::NumTargetFixupKinds;
|
|
}
|
|
|
|
/// @name Target Relaxation Interfaces
|
|
/// @{
|
|
|
|
/// fixupNeedsRelaxation - Target specific predicate for whether a given
|
|
/// fixup requires the associated instruction to be relaxed.
|
|
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
|
|
const MCRelaxableFragment *DF,
|
|
const MCAsmLayout &Layout) const override {
|
|
// FIXME.
|
|
llvm_unreachable("RelaxInstruction() unimplemented");
|
|
return false;
|
|
}
|
|
|
|
bool writeNopData(raw_ostream &OS, uint64_t Count,
|
|
const MCSubtargetInfo *STI) const override;
|
|
|
|
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
|
|
const MCValue &Target) override;
|
|
|
|
bool isMicroMips(const MCSymbol *Sym) const override;
|
|
}; // class MipsAsmBackend
|
|
|
|
} // namespace
|
|
|
|
#endif
|