Alexander Shaposhnikov 6cf10b7e6e [InstCombine] Fold srem(X, PowerOf2) == C into (X & Mask) == C for positive C ...

This diff extends InstCombinerImpl::foldICmpSRemConstant to handle the cases
srem(X, PowerOf2) == C and
srem(X, PowerOf2) != C
for positive C.
This addresses the issue https://github.com/llvm/llvm-project/issues/54650

Differential revision: https://reviews.llvm.org/D122942

Test plan: make check-all

2022-04-03 03:57:05 +00:00

..

CMakeLists.txt

llvmbuildectomy - replace llvm-build by plain cmake

2020-11-13 10:35:24 +01:00

InstCombineAddSub.cpp

[NFCI] Fix set-but-unused warning in InstCombineAddSub.cpp

2022-03-24 08:33:40 +01:00

InstCombineAndOrXor.cpp

[InstCombine] Fold (X | C2) ^ C1 --> (X & ~C2) ^ (C1^C2)

2022-04-03 00:12:56 +03:00

InstCombineAtomicRMW.cpp

Cleanup includes: Transform/Scalar

2022-03-03 07:56:34 +01:00

InstCombineCalls.cpp

[InstCombine] Remove call to getPointerElementType()

2022-03-29 16:52:29 +02:00

InstCombineCasts.cpp

Cleanup includes: Transform/Scalar

2022-03-03 07:56:34 +01:00

InstCombineCompares.cpp

[InstCombine] Fold srem(X, PowerOf2) == C into (X & Mask) == C for positive C

2022-04-03 03:57:05 +00:00

InstCombineInternal.h

[InstCombine] Fold select based logic of fcmps with same operands when FMF is present.

2022-03-14 14:45:07 -07:00

InstCombineLoadStoreAlloca.cpp

Cleanup includes: Transform/Scalar

2022-03-03 07:56:34 +01:00

InstCombineMulDivRem.cpp

Cleanup includes: Transform/Scalar

2022-03-03 07:56:34 +01:00

InstCombineNegator.cpp

[InstCombine] Fold sub(Y,and(lshr(X,C),1)) --> add(ashr(shl(X,(BW-1)-C),BW-1),Y) (PR53610)

2022-02-15 13:24:20 +00:00

InstCombinePHI.cpp

Reapply [InstCombine] Support switch in phi to cond fold

2022-03-17 10:03:09 +01:00

InstCombineSelect.cpp

[InstCombine] Fold two select patterns into and-or

2022-03-28 16:07:55 -04:00

InstCombineShifts.cpp

[InstCombine] try to narrow shifted bswap-of-zext (2nd try)

2022-03-23 11:28:37 -04:00

InstCombineSimplifyDemanded.cpp

[InstCombine] SimplifyDemandedUseBits - remove ashr node if we only demand known sign bits

2022-03-25 15:39:08 +00:00

InstCombineVectorOps.cpp

[InstCombine] merge shuffled vector negate and multiply

2022-03-24 10:25:16 -04:00

InstructionCombining.cpp

[InstCombine] Sink instructions with multiple users in a successor block.

2022-03-18 11:53:45 +08:00