adec922361
We would like to start pushing -mcpu=generic towards enabling the set of features that improves performance for some CPUs, without hurting any others. A blend of the performance options hopefully beneficial to all CPUs. The largest part of that is enabling in-order scheduling using the Cortex-A55 schedule model. This is similar to the Arm backend change from eecb353d0e25ba which made -mcpu=generic perform in-order scheduling using the cortex-a8 schedule model. The idea is that in-order cpu's require the most help in instruction scheduling, whereas out-of-order cpus can for the most part out-of-order schedule around different codegen. Our benchmarking suggests that hypothesis holds. When running on an in-order core this improved performance by 3.8% geomean on a set of DSP workloads, 2% geomean on some other embedded benchmark and between 1% and 1.8% on a set of singlecore and multicore workloads, all running on a Cortex-A55 cluster. On an out-of-order cpu the results are a lot more noisy but show flat performance or an improvement. On the set of DSP and embedded benchmarks, run on a Cortex-A78 there was a very noisy 1% speed improvement. Using the most detailed results I could find, SPEC2006 runs on a Neoverse N1 show a small increase in instruction count (+0.127%), but a decrease in cycle counts (-0.155%, on average). The instruction count is very low noise, the cycle count is more noisy with a 0.15% decrease not being significant. SPEC2k17 shows a small decrease (-0.2%) in instruction count leading to a -0.296% decrease in cycle count. These results are within noise margins but tend to show a small improvement in general. When specifying an Apple target, clang will set "-target-cpu apple-a7" on the command line, so should not be affected by this change when running from clang. This also doesn't enable more runtime unrolling like -mcpu=cortex-a55 does, only changing the schedule used. A lot of existing tests have updated. This is a summary of the important differences: - Most changes are the same instructions in a different order. - Sometimes this leads to very minor inefficiencies, such as requiring an extra mov to move variables into r0/v0 for the return value of a test function. - misched-fusion.ll was no longer fusing the pairs of instructions it should, as per D110561. I've changed the schedule used in the test for now. - neon-mla-mls.ll now uses "mul; sub" as opposed to "neg; mla" due to the different latencies. This seems fine to me. - Some SVE tests do not always remove movprfx where they did before due to different register allocation giving different destructive forms. - The tests argument-blocks-array-of-struct.ll and arm64-windows-calls.ll produce two LDR where they previously produced an LDP due to store-pair-suppress kicking in. - arm64-ldp.ll and arm64-neon-copy.ll are missing pre/postinc on LPD. - Some tests such as arm64-neon-mul-div.ll and ragreedy-local-interval-cost.ll have more, less or just different spilling. - In aarch64_generated_funcs.ll.generated.expected one part of the function is no longer outlined. Interestingly if I switch this to use any other scheduled even less is outlined. Some of these are expected to happen, such as differences in outlining or register spilling. There will be places where these result in worse codegen, places where they are better, with the SPEC instruction counts suggesting it is not a decrease overall, on average. Differential Revision: https://reviews.llvm.org/D110830
115 lines
4.0 KiB
LLVM
115 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+lsl-fast | FileCheck %s
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%struct.a = type [256 x i16]
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%struct.b = type [256 x i32]
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%struct.c = type [256 x i64]
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declare void @foo()
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define i16 @halfword(%struct.a* %ctx, i32 %xor72) nounwind {
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; CHECK-LABEL: halfword:
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; CHECK: // %bb.0:
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; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
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; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: ubfx x21, x1, #9, #8
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; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: mov x19, x0
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; CHECK-NEXT: ldrh w20, [x0, x21, lsl #1]
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; CHECK-NEXT: bl foo
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; CHECK-NEXT: mov w0, w20
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; CHECK-NEXT: strh w20, [x19, x21, lsl #1]
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; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload
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; CHECK-NEXT: ret
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%shr81 = lshr i32 %xor72, 9
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%conv82 = zext i32 %shr81 to i64
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%idxprom83 = and i64 %conv82, 255
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%arrayidx86 = getelementptr inbounds %struct.a, %struct.a* %ctx, i64 0, i64 %idxprom83
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%result = load i16, i16* %arrayidx86, align 2
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call void @foo()
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store i16 %result, i16* %arrayidx86, align 2
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ret i16 %result
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}
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define i32 @word(%struct.b* %ctx, i32 %xor72) nounwind {
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; CHECK-LABEL: word:
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; CHECK: // %bb.0:
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; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
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; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: ubfx x21, x1, #9, #8
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; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: mov x19, x0
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; CHECK-NEXT: ldr w20, [x0, x21, lsl #2]
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; CHECK-NEXT: bl foo
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; CHECK-NEXT: mov w0, w20
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; CHECK-NEXT: str w20, [x19, x21, lsl #2]
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; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload
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; CHECK-NEXT: ret
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%shr81 = lshr i32 %xor72, 9
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%conv82 = zext i32 %shr81 to i64
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%idxprom83 = and i64 %conv82, 255
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%arrayidx86 = getelementptr inbounds %struct.b, %struct.b* %ctx, i64 0, i64 %idxprom83
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%result = load i32, i32* %arrayidx86, align 4
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call void @foo()
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store i32 %result, i32* %arrayidx86, align 4
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ret i32 %result
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}
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define i64 @doubleword(%struct.c* %ctx, i32 %xor72) nounwind {
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; CHECK-LABEL: doubleword:
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; CHECK: // %bb.0:
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; CHECK-NEXT: stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
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; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: ubfx x21, x1, #9, #8
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; CHECK-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: mov x19, x0
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; CHECK-NEXT: ldr x20, [x0, x21, lsl #3]
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; CHECK-NEXT: bl foo
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; CHECK-NEXT: mov x0, x20
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; CHECK-NEXT: str x20, [x19, x21, lsl #3]
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; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: ldp x30, x21, [sp], #32 // 16-byte Folded Reload
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; CHECK-NEXT: ret
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%shr81 = lshr i32 %xor72, 9
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%conv82 = zext i32 %shr81 to i64
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%idxprom83 = and i64 %conv82, 255
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%arrayidx86 = getelementptr inbounds %struct.c, %struct.c* %ctx, i64 0, i64 %idxprom83
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%result = load i64, i64* %arrayidx86, align 8
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call void @foo()
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store i64 %result, i64* %arrayidx86, align 8
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ret i64 %result
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}
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define i64 @multi_use_non_memory(i64 %a, i64 %b) {
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; CHECK-LABEL: multi_use_non_memory:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: lsl x8, x0, #3
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; CHECK-NEXT: lsl x9, x1, #3
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; CHECK-NEXT: cmp x8, x9
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; CHECK-NEXT: b.lt .LBB3_2
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; CHECK-NEXT: // %bb.1: // %falsebb
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; CHECK-NEXT: csel x0, x8, x9, gt
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB3_2: // %truebb
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; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: bl foo
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entry:
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%mul1 = shl i64 %a, 3
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%mul2 = shl i64 %b, 3
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%cmp = icmp slt i64 %mul1, %mul2
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br i1 %cmp, label %truebb, label %falsebb
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truebb:
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tail call void @foo()
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unreachable
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falsebb:
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%cmp2 = icmp sgt i64 %mul1, %mul2
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br i1 %cmp2, label %exitbb, label %endbb
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exitbb:
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ret i64 %mul1
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endbb:
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ret i64 %mul2
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}
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