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llvm-project/llvm/test/CodeGen/AArch64/nontemporal.ll
David Green adec922361 [AArch64] Make -mcpu=generic schedule for an in-order core 
We would like to start pushing -mcpu=generic towards enabling the set of
features that improves performance for some CPUs, without hurting any
others. A blend of the performance options hopefully beneficial to all
CPUs. The largest part of that is enabling in-order scheduling using the
Cortex-A55 schedule model. This is similar to the Arm backend change
from eecb353d0e25ba which made -mcpu=generic perform in-order scheduling
using the cortex-a8 schedule model.

The idea is that in-order cpu's require the most help in instruction
scheduling, whereas out-of-order cpus can for the most part out-of-order
schedule around different codegen. Our benchmarking suggests that
hypothesis holds. When running on an in-order core this improved
performance by 3.8% geomean on a set of DSP workloads, 2% geomean on
some other embedded benchmark and between 1% and 1.8% on a set of
singlecore and multicore workloads, all running on a Cortex-A55 cluster.

On an out-of-order cpu the results are a lot more noisy but show flat
performance or an improvement. On the set of DSP and embedded
benchmarks, run on a Cortex-A78 there was a very noisy 1% speed
improvement. Using the most detailed results I could find, SPEC2006 runs
on a Neoverse N1 show a small increase in instruction count (+0.127%),
but a decrease in cycle counts (-0.155%, on average). The instruction
count is very low noise, the cycle count is more noisy with a 0.15%
decrease not being significant. SPEC2k17 shows a small decrease (-0.2%)
in instruction count leading to a -0.296% decrease in cycle count. These
results are within noise margins but tend to show a small improvement in
general.

When specifying an Apple target, clang will set "-target-cpu apple-a7"
on the command line, so should not be affected by this change when
running from clang. This also doesn't enable more runtime unrolling like
-mcpu=cortex-a55 does, only changing the schedule used.

A lot of existing tests have updated. This is a summary of the important
differences:
 - Most changes are the same instructions in a different order.
 - Sometimes this leads to very minor inefficiencies, such as requiring
   an extra mov to move variables into r0/v0 for the return value of a test
   function.
 - misched-fusion.ll was no longer fusing the pairs of instructions it
   should, as per D110561. I've changed the schedule used in the test
   for now.
 - neon-mla-mls.ll now uses "mul; sub" as opposed to "neg; mla" due to
   the different latencies. This seems fine to me.
 - Some SVE tests do not always remove movprfx where they did before due
   to different register allocation giving different destructive forms.
 - The tests argument-blocks-array-of-struct.ll and arm64-windows-calls.ll
   produce two LDR where they previously produced an LDP due to
   store-pair-suppress kicking in.
 - arm64-ldp.ll and arm64-neon-copy.ll are missing pre/postinc on LPD.
 - Some tests such as arm64-neon-mul-div.ll and
   ragreedy-local-interval-cost.ll have more, less or just different
   spilling.
 - In aarch64_generated_funcs.ll.generated.expected one part of the
   function is no longer outlined. Interestingly if I switch this to use
   any other scheduled even less is outlined.

Some of these are expected to happen, such as differences in outlining
or register spilling. There will be places where these result in worse
codegen, places where they are better, with the SPEC instruction counts
suggesting it is not a decrease overall, on average.

Differential Revision: https://reviews.llvm.org/D110830
2021-10-09 15:58:31 +01:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple aarch64-apple-darwin | FileCheck %s
define void @test_stnp_v4i64(<4 x i64>* %p, <4 x i64> %v) #0 {
; CHECK-LABEL: test_stnp_v4i64:
; CHECK: ; %bb.0:
; CHECK-NEXT: stnp q0, q1, [x0]
; CHECK-NEXT: ret
store <4 x i64> %v, <4 x i64>* %p, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v4i32(<4 x i32>* %p, <4 x i32> %v) #0 {
; CHECK-LABEL: test_stnp_v4i32:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov d1, v0[1]
; CHECK-NEXT: stnp d0, d1, [x0]
; CHECK-NEXT: ret
store <4 x i32> %v, <4 x i32>* %p, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v8i16(<8 x i16>* %p, <8 x i16> %v) #0 {
; CHECK-LABEL: test_stnp_v8i16:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov d1, v0[1]
; CHECK-NEXT: stnp d0, d1, [x0]
; CHECK-NEXT: ret
store <8 x i16> %v, <8 x i16>* %p, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v16i8(<16 x i8>* %p, <16 x i8> %v) #0 {
; CHECK-LABEL: test_stnp_v16i8:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov d1, v0[1]
; CHECK-NEXT: stnp d0, d1, [x0]
; CHECK-NEXT: ret
store <16 x i8> %v, <16 x i8>* %p, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v2i32(<2 x i32>* %p, <2 x i32> %v) #0 {
; CHECK-LABEL: test_stnp_v2i32:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov s1, v0[1]
; CHECK-NEXT: stnp s0, s1, [x0]
; CHECK-NEXT: ret
store <2 x i32> %v, <2 x i32>* %p, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v4i16(<4 x i16>* %p, <4 x i16> %v) #0 {
; CHECK-LABEL: test_stnp_v4i16:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov s1, v0[1]
; CHECK-NEXT: stnp s0, s1, [x0]
; CHECK-NEXT: ret
store <4 x i16> %v, <4 x i16>* %p, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v8i8(<8 x i8>* %p, <8 x i8> %v) #0 {
; CHECK-LABEL: test_stnp_v8i8:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov s1, v0[1]
; CHECK-NEXT: stnp s0, s1, [x0]
; CHECK-NEXT: ret
store <8 x i8> %v, <8 x i8>* %p, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v2f64(<2 x double>* %p, <2 x double> %v) #0 {
; CHECK-LABEL: test_stnp_v2f64:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov d1, v0[1]
; CHECK-NEXT: stnp d0, d1, [x0]
; CHECK-NEXT: ret
store <2 x double> %v, <2 x double>* %p, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v4f32(<4 x float>* %p, <4 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v4f32:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov d1, v0[1]
; CHECK-NEXT: stnp d0, d1, [x0]
; CHECK-NEXT: ret
store <4 x float> %v, <4 x float>* %p, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v2f32(<2 x float>* %p, <2 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v2f32:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov s1, v0[1]
; CHECK-NEXT: stnp s0, s1, [x0]
; CHECK-NEXT: ret
store <2 x float> %v, <2 x float>* %p, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v1f64(<1 x double>* %p, <1 x double> %v) #0 {
; CHECK-LABEL: test_stnp_v1f64:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov s1, v0[1]
; CHECK-NEXT: stnp s0, s1, [x0]
; CHECK-NEXT: ret
store <1 x double> %v, <1 x double>* %p, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v1i64(<1 x i64>* %p, <1 x i64> %v) #0 {
; CHECK-LABEL: test_stnp_v1i64:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov s1, v0[1]
; CHECK-NEXT: stnp s0, s1, [x0]
; CHECK-NEXT: ret
store <1 x i64> %v, <1 x i64>* %p, align 1, !nontemporal !0
ret void
}
define void @test_stnp_i64(i64* %p, i64 %v) #0 {
; CHECK-LABEL: test_stnp_i64:
; CHECK: ; %bb.0:
; CHECK-NEXT: lsr x8, x1, #32
; CHECK-NEXT: stnp w1, w8, [x0]
; CHECK-NEXT: ret
store i64 %v, i64* %p, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v2f64_offset(<2 x double>* %p, <2 x double> %v) #0 {
; CHECK-LABEL: test_stnp_v2f64_offset:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov d1, v0[1]
; CHECK-NEXT: stnp d0, d1, [x0, #16]
; CHECK-NEXT: ret
%tmp0 = getelementptr <2 x double>, <2 x double>* %p, i32 1
store <2 x double> %v, <2 x double>* %tmp0, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v2f64_offset_neg(<2 x double>* %p, <2 x double> %v) #0 {
; CHECK-LABEL: test_stnp_v2f64_offset_neg:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov d1, v0[1]
; CHECK-NEXT: stnp d0, d1, [x0, #-16]
; CHECK-NEXT: ret
%tmp0 = getelementptr <2 x double>, <2 x double>* %p, i32 -1
store <2 x double> %v, <2 x double>* %tmp0, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v2f32_offset(<2 x float>* %p, <2 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v2f32_offset:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov s1, v0[1]
; CHECK-NEXT: stnp s0, s1, [x0, #8]
; CHECK-NEXT: ret
%tmp0 = getelementptr <2 x float>, <2 x float>* %p, i32 1
store <2 x float> %v, <2 x float>* %tmp0, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v2f32_offset_neg(<2 x float>* %p, <2 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v2f32_offset_neg:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov s1, v0[1]
; CHECK-NEXT: stnp s0, s1, [x0, #-8]
; CHECK-NEXT: ret
%tmp0 = getelementptr <2 x float>, <2 x float>* %p, i32 -1
store <2 x float> %v, <2 x float>* %tmp0, align 1, !nontemporal !0
ret void
}
define void @test_stnp_i64_offset(i64* %p, i64 %v) #0 {
; CHECK-LABEL: test_stnp_i64_offset:
; CHECK: ; %bb.0:
; CHECK-NEXT: lsr x8, x1, #32
; CHECK-NEXT: stnp w1, w8, [x0, #8]
; CHECK-NEXT: ret
%tmp0 = getelementptr i64, i64* %p, i32 1
store i64 %v, i64* %tmp0, align 1, !nontemporal !0
ret void
}
define void @test_stnp_i64_offset_neg(i64* %p, i64 %v) #0 {
; CHECK-LABEL: test_stnp_i64_offset_neg:
; CHECK: ; %bb.0:
; CHECK-NEXT: lsr x8, x1, #32
; CHECK-NEXT: stnp w1, w8, [x0, #-8]
; CHECK-NEXT: ret
%tmp0 = getelementptr i64, i64* %p, i32 -1
store i64 %v, i64* %tmp0, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v4f32_invalid_offset_4(i8* %p, <4 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v4f32_invalid_offset_4:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov d1, v0[1]
; CHECK-NEXT: add x8, x0, #4
; CHECK-NEXT: stnp d0, d1, [x8]
; CHECK-NEXT: ret
%tmp0 = getelementptr i8, i8* %p, i32 4
%tmp1 = bitcast i8* %tmp0 to <4 x float>*
store <4 x float> %v, <4 x float>* %tmp1, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v4f32_invalid_offset_neg_4(i8* %p, <4 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v4f32_invalid_offset_neg_4:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov d1, v0[1]
; CHECK-NEXT: sub x8, x0, #4
; CHECK-NEXT: stnp d0, d1, [x8]
; CHECK-NEXT: ret
%tmp0 = getelementptr i8, i8* %p, i32 -4
%tmp1 = bitcast i8* %tmp0 to <4 x float>*
store <4 x float> %v, <4 x float>* %tmp1, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v4f32_invalid_offset_512(i8* %p, <4 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v4f32_invalid_offset_512:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov d1, v0[1]
; CHECK-NEXT: add x8, x0, #512
; CHECK-NEXT: stnp d0, d1, [x8]
; CHECK-NEXT: ret
%tmp0 = getelementptr i8, i8* %p, i32 512
%tmp1 = bitcast i8* %tmp0 to <4 x float>*
store <4 x float> %v, <4 x float>* %tmp1, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v4f32_offset_504(i8* %p, <4 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v4f32_offset_504:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov d1, v0[1]
; CHECK-NEXT: stnp d0, d1, [x0, #504]
; CHECK-NEXT: ret
%tmp0 = getelementptr i8, i8* %p, i32 504
%tmp1 = bitcast i8* %tmp0 to <4 x float>*
store <4 x float> %v, <4 x float>* %tmp1, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v4f32_invalid_offset_508(i8* %p, <4 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v4f32_invalid_offset_508:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov d1, v0[1]
; CHECK-NEXT: add x8, x0, #508
; CHECK-NEXT: stnp d0, d1, [x8]
; CHECK-NEXT: ret
%tmp0 = getelementptr i8, i8* %p, i32 508
%tmp1 = bitcast i8* %tmp0 to <4 x float>*
store <4 x float> %v, <4 x float>* %tmp1, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v4f32_invalid_offset_neg_520(i8* %p, <4 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v4f32_invalid_offset_neg_520:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov d1, v0[1]
; CHECK-NEXT: sub x8, x0, #520
; CHECK-NEXT: stnp d0, d1, [x8]
; CHECK-NEXT: ret
%tmp0 = getelementptr i8, i8* %p, i32 -520
%tmp1 = bitcast i8* %tmp0 to <4 x float>*
store <4 x float> %v, <4 x float>* %tmp1, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v4f32_offset_neg_512(i8* %p, <4 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v4f32_offset_neg_512:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov d1, v0[1]
; CHECK-NEXT: stnp d0, d1, [x0, #-512]
; CHECK-NEXT: ret
%tmp0 = getelementptr i8, i8* %p, i32 -512
%tmp1 = bitcast i8* %tmp0 to <4 x float>*
store <4 x float> %v, <4 x float>* %tmp1, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v2f32_invalid_offset_256(i8* %p, <2 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v2f32_invalid_offset_256:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov s1, v0[1]
; CHECK-NEXT: add x8, x0, #256
; CHECK-NEXT: stnp s0, s1, [x8]
; CHECK-NEXT: ret
%tmp0 = getelementptr i8, i8* %p, i32 256
%tmp1 = bitcast i8* %tmp0 to <2 x float>*
store <2 x float> %v, <2 x float>* %tmp1, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v2f32_offset_252(i8* %p, <2 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v2f32_offset_252:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov s1, v0[1]
; CHECK-NEXT: stnp s0, s1, [x0, #252]
; CHECK-NEXT: ret
%tmp0 = getelementptr i8, i8* %p, i32 252
%tmp1 = bitcast i8* %tmp0 to <2 x float>*
store <2 x float> %v, <2 x float>* %tmp1, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v2f32_invalid_offset_neg_260(i8* %p, <2 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v2f32_invalid_offset_neg_260:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov s1, v0[1]
; CHECK-NEXT: sub x8, x0, #260
; CHECK-NEXT: stnp s0, s1, [x8]
; CHECK-NEXT: ret
%tmp0 = getelementptr i8, i8* %p, i32 -260
%tmp1 = bitcast i8* %tmp0 to <2 x float>*
store <2 x float> %v, <2 x float>* %tmp1, align 1, !nontemporal !0
ret void
}
define void @test_stnp_v2f32_offset_neg_256(i8* %p, <2 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v2f32_offset_neg_256:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov s1, v0[1]
; CHECK-NEXT: stnp s0, s1, [x0, #-256]
; CHECK-NEXT: ret
%tmp0 = getelementptr i8, i8* %p, i32 -256
%tmp1 = bitcast i8* %tmp0 to <2 x float>*
store <2 x float> %v, <2 x float>* %tmp1, align 1, !nontemporal !0
ret void
}
declare void @dummy(<4 x float>*)
define void @test_stnp_v4f32_offset_alloca(<4 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v4f32_offset_alloca:
; CHECK: ; %bb.0:
; CHECK-NEXT: sub sp, sp, #32
; CHECK-NEXT: mov d1, v0[1]
; CHECK-NEXT: mov x0, sp
; CHECK-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; CHECK-NEXT: stnp d0, d1, [sp]
; CHECK-NEXT: bl _dummy
; CHECK-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #32
; CHECK-NEXT: ret
%tmp0 = alloca <4 x float>
store <4 x float> %v, <4 x float>* %tmp0, align 1, !nontemporal !0
call void @dummy(<4 x float>* %tmp0)
ret void
}
define void @test_stnp_v4f32_offset_alloca_2(<4 x float> %v) #0 {
; CHECK-LABEL: test_stnp_v4f32_offset_alloca_2:
; CHECK: ; %bb.0:
; CHECK-NEXT: sub sp, sp, #48
; CHECK-NEXT: mov d1, v0[1]
; CHECK-NEXT: mov x0, sp
; CHECK-NEXT: stp x29, x30, [sp, #32] ; 16-byte Folded Spill
; CHECK-NEXT: stnp d0, d1, [sp, #16]
; CHECK-NEXT: bl _dummy
; CHECK-NEXT: ldp x29, x30, [sp, #32] ; 16-byte Folded Reload
; CHECK-NEXT: add sp, sp, #48
; CHECK-NEXT: ret
%tmp0 = alloca <4 x float>, i32 2
%tmp1 = getelementptr <4 x float>, <4 x float>* %tmp0, i32 1
store <4 x float> %v, <4 x float>* %tmp1, align 1, !nontemporal !0
call void @dummy(<4 x float>* %tmp0)
ret void
}
define void @test_stnp_v32i8(<32 x i8> %v, <32 x i8>* %ptr) {
; CHECK-LABEL: test_stnp_v32i8:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: stnp q0, q1, [x0]
; CHECK-NEXT: ret
entry:
store <32 x i8> %v, <32 x i8>* %ptr, align 4, !nontemporal !0
ret void
}
define void @test_stnp_v32i16(<32 x i16> %v, <32 x i16>* %ptr) {
; CHECK-LABEL: test_stnp_v32i16:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: stnp q2, q3, [x0, #32]
; CHECK-NEXT: stnp q0, q1, [x0]
; CHECK-NEXT: ret
entry:
store <32 x i16> %v, <32 x i16>* %ptr, align 4, !nontemporal !0
ret void
}
define void @test_stnp_v32f16(<32 x half> %v, <32 x half>* %ptr) {
; CHECK-LABEL: test_stnp_v32f16:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: stnp q2, q3, [x0, #32]
; CHECK-NEXT: stnp q0, q1, [x0]
; CHECK-NEXT: ret
entry:
store <32 x half> %v, <32 x half>* %ptr, align 4, !nontemporal !0
ret void
}
define void @test_stnp_v16i32(<16 x i32> %v, <16 x i32>* %ptr) {
; CHECK-LABEL: test_stnp_v16i32:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: stnp q2, q3, [x0, #32]
; CHECK-NEXT: stnp q0, q1, [x0]
; CHECK-NEXT: ret
entry:
store <16 x i32> %v, <16 x i32>* %ptr, align 4, !nontemporal !0
ret void
}
define void @test_stnp_v16f32(<16 x float> %v, <16 x float>* %ptr) {
; CHECK-LABEL: test_stnp_v16f32:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: stnp q2, q3, [x0, #32]
; CHECK-NEXT: stnp q0, q1, [x0]
; CHECK-NEXT: ret
entry:
store <16 x float> %v, <16 x float>* %ptr, align 4, !nontemporal !0
ret void
}
define void @test_stnp_v17f32(<17 x float> %v, <17 x float>* %ptr) {
; CHECK-LABEL: test_stnp_v17f32:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: ldr s16, [sp, #16]
; CHECK-NEXT: add x8, sp, #20
; CHECK-NEXT: ldr s17, [sp]
; CHECK-NEXT: add x9, sp, #4
; CHECK-NEXT: ; kill: def $s4 killed $s4 def $q4
; CHECK-NEXT: ; kill: def $s0 killed $s0 def $q0
; CHECK-NEXT: ; kill: def $s5 killed $s5 def $q5
; CHECK-NEXT: ; kill: def $s1 killed $s1 def $q1
; CHECK-NEXT: ; kill: def $s6 killed $s6 def $q6
; CHECK-NEXT: ; kill: def $s2 killed $s2 def $q2
; CHECK-NEXT: ; kill: def $s7 killed $s7 def $q7
; CHECK-NEXT: ; kill: def $s3 killed $s3 def $q3
; CHECK-NEXT: ld1.s { v16 }[1], [x8]
; CHECK-NEXT: add x8, sp, #24
; CHECK-NEXT: ld1.s { v17 }[1], [x9]
; CHECK-NEXT: add x9, sp, #8
; CHECK-NEXT: mov.s v4[1], v5[0]
; CHECK-NEXT: mov.s v0[1], v1[0]
; CHECK-NEXT: ld1.s { v16 }[2], [x8]
; CHECK-NEXT: add x8, sp, #28
; CHECK-NEXT: ld1.s { v17 }[2], [x9]
; CHECK-NEXT: add x9, sp, #12
; CHECK-NEXT: mov.s v4[2], v6[0]
; CHECK-NEXT: mov.s v0[2], v2[0]
; CHECK-NEXT: ld1.s { v16 }[3], [x8]
; CHECK-NEXT: ld1.s { v17 }[3], [x9]
; CHECK-NEXT: mov.s v4[3], v7[0]
; CHECK-NEXT: mov.s v0[3], v3[0]
; CHECK-NEXT: mov d1, v16[1]
; CHECK-NEXT: mov d2, v17[1]
; CHECK-NEXT: mov d3, v4[1]
; CHECK-NEXT: mov d5, v0[1]
; CHECK-NEXT: stnp d16, d1, [x0, #48]
; CHECK-NEXT: ldr s1, [sp, #32]
; CHECK-NEXT: stnp d17, d2, [x0, #32]
; CHECK-NEXT: stnp d4, d3, [x0, #16]
; CHECK-NEXT: stnp d0, d5, [x0]
; CHECK-NEXT: str s1, [x0, #64]
; CHECK-NEXT: ret
entry:
store <17 x float> %v, <17 x float>* %ptr, align 4, !nontemporal !0
ret void
}
define void @test_stnp_v16i32_invalid_offset(<16 x i32> %v, <16 x i32>* %ptr) {
; CHECK-LABEL: test_stnp_v16i32_invalid_offset:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: mov w8, #32032
; CHECK-NEXT: mov w9, #32000
; CHECK-NEXT: add x8, x0, x8
; CHECK-NEXT: add x9, x0, x9
; CHECK-NEXT: stnp q2, q3, [x8]
; CHECK-NEXT: stnp q0, q1, [x9]
; CHECK-NEXT: ret
entry:
%gep = getelementptr <16 x i32>, <16 x i32>* %ptr, i32 500
store <16 x i32> %v, <16 x i32>* %gep, align 4, !nontemporal !0
ret void
}
define void @test_stnp_v16f64(<16 x double> %v, <16 x double>* %ptr) {
; CHECK-LABEL: test_stnp_v16f64:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: stnp q6, q7, [x0, #96]
; CHECK-NEXT: stnp q4, q5, [x0, #64]
; CHECK-NEXT: stnp q2, q3, [x0, #32]
; CHECK-NEXT: stnp q0, q1, [x0]
; CHECK-NEXT: ret
entry:
store <16 x double> %v, <16 x double>* %ptr, align 4, !nontemporal !0
ret void
}
define void @test_stnp_v16i64(<16 x i64> %v, <16 x i64>* %ptr) {
; CHECK-LABEL: test_stnp_v16i64:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: stnp q6, q7, [x0, #96]
; CHECK-NEXT: stnp q4, q5, [x0, #64]
; CHECK-NEXT: stnp q2, q3, [x0, #32]
; CHECK-NEXT: stnp q0, q1, [x0]
; CHECK-NEXT: ret
entry:
store <16 x i64> %v, <16 x i64>* %ptr, align 4, !nontemporal !0
ret void
}
!0 = !{ i32 1 }
attributes #0 = { nounwind }
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