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llvm-project/llvm/test/CodeGen/AArch64/reduce-or.ll
David Green adec922361 [AArch64] Make -mcpu=generic schedule for an in-order core 
We would like to start pushing -mcpu=generic towards enabling the set of
features that improves performance for some CPUs, without hurting any
others. A blend of the performance options hopefully beneficial to all
CPUs. The largest part of that is enabling in-order scheduling using the
Cortex-A55 schedule model. This is similar to the Arm backend change
from eecb353d0e25ba which made -mcpu=generic perform in-order scheduling
using the cortex-a8 schedule model.

The idea is that in-order cpu's require the most help in instruction
scheduling, whereas out-of-order cpus can for the most part out-of-order
schedule around different codegen. Our benchmarking suggests that
hypothesis holds. When running on an in-order core this improved
performance by 3.8% geomean on a set of DSP workloads, 2% geomean on
some other embedded benchmark and between 1% and 1.8% on a set of
singlecore and multicore workloads, all running on a Cortex-A55 cluster.

On an out-of-order cpu the results are a lot more noisy but show flat
performance or an improvement. On the set of DSP and embedded
benchmarks, run on a Cortex-A78 there was a very noisy 1% speed
improvement. Using the most detailed results I could find, SPEC2006 runs
on a Neoverse N1 show a small increase in instruction count (+0.127%),
but a decrease in cycle counts (-0.155%, on average). The instruction
count is very low noise, the cycle count is more noisy with a 0.15%
decrease not being significant. SPEC2k17 shows a small decrease (-0.2%)
in instruction count leading to a -0.296% decrease in cycle count. These
results are within noise margins but tend to show a small improvement in
general.

When specifying an Apple target, clang will set "-target-cpu apple-a7"
on the command line, so should not be affected by this change when
running from clang. This also doesn't enable more runtime unrolling like
-mcpu=cortex-a55 does, only changing the schedule used.

A lot of existing tests have updated. This is a summary of the important
differences:
 - Most changes are the same instructions in a different order.
 - Sometimes this leads to very minor inefficiencies, such as requiring
   an extra mov to move variables into r0/v0 for the return value of a test
   function.
 - misched-fusion.ll was no longer fusing the pairs of instructions it
   should, as per D110561. I've changed the schedule used in the test
   for now.
 - neon-mla-mls.ll now uses "mul; sub" as opposed to "neg; mla" due to
   the different latencies. This seems fine to me.
 - Some SVE tests do not always remove movprfx where they did before due
   to different register allocation giving different destructive forms.
 - The tests argument-blocks-array-of-struct.ll and arm64-windows-calls.ll
   produce two LDR where they previously produced an LDP due to
   store-pair-suppress kicking in.
 - arm64-ldp.ll and arm64-neon-copy.ll are missing pre/postinc on LPD.
 - Some tests such as arm64-neon-mul-div.ll and
   ragreedy-local-interval-cost.ll have more, less or just different
   spilling.
 - In aarch64_generated_funcs.ll.generated.expected one part of the
   function is no longer outlined. Interestingly if I switch this to use
   any other scheduled even less is outlined.

Some of these are expected to happen, such as differences in outlining
or register spilling. There will be places where these result in worse
codegen, places where they are better, with the SPEC instruction counts
suggesting it is not a decrease overall, on average.

Differential Revision: https://reviews.llvm.org/D110830
2021-10-09 15:58:31 +01:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=1 | FileCheck %s --check-prefix=GISEL
define i1 @test_redor_v1i1(<1 x i1> %a) {
; CHECK-LABEL: test_redor_v1i1:
; CHECK: // %bb.0:
; CHECK-NEXT: and w0, w0, #0x1
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v1i1:
; GISEL: // %bb.0:
; GISEL-NEXT: and w0, w0, #0x1
; GISEL-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %a)
ret i1 %or_result
}
define i1 @test_redor_v2i1(<2 x i1> %a) {
; CHECK-LABEL: test_redor_v2i1:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v2i1:
; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov s1, v0.s[1]
; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: and w0, w8, #0x1
; GISEL-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %a)
ret i1 %or_result
}
define i1 @test_redor_v4i1(<4 x i1> %a) {
; CHECK-LABEL: test_redor_v4i1:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: umov w9, v0.h[0]
; CHECK-NEXT: umov w10, v0.h[2]
; CHECK-NEXT: umov w11, v0.h[3]
; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: orr w8, w8, w11
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v4i1:
; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov h1, v0.h[1]
; GISEL-NEXT: mov h2, v0.h[2]
; GISEL-NEXT: mov h3, v0.h[3]
; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: fmov w10, s2
; GISEL-NEXT: fmov w11, s3
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: orr w9, w10, w11
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: and w0, w8, #0x1
; GISEL-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %a)
ret i1 %or_result
}
define i1 @test_redor_v8i1(<8 x i1> %a) {
; CHECK-LABEL: test_redor_v8i1:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: umov w13, v0.b[5]
; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[6]
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[7]
; CHECK-NEXT: orr w8, w8, w11
; CHECK-NEXT: orr w8, w8, w12
; CHECK-NEXT: orr w8, w8, w13
; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v8i1:
; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2]
; GISEL-NEXT: mov b3, v0.b[3]
; GISEL-NEXT: mov b4, v0.b[4]
; GISEL-NEXT: mov b5, v0.b[5]
; GISEL-NEXT: mov b6, v0.b[6]
; GISEL-NEXT: mov b7, v0.b[7]
; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: fmov w10, s2
; GISEL-NEXT: fmov w11, s3
; GISEL-NEXT: fmov w12, s4
; GISEL-NEXT: fmov w13, s5
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: fmov w9, s6
; GISEL-NEXT: orr w10, w10, w11
; GISEL-NEXT: fmov w11, s7
; GISEL-NEXT: orr w12, w12, w13
; GISEL-NEXT: orr w8, w8, w10
; GISEL-NEXT: orr w9, w9, w11
; GISEL-NEXT: orr w9, w12, w9
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: and w0, w8, #0x1
; GISEL-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> %a)
ret i1 %or_result
}
define i1 @test_redor_v16i1(<16 x i1> %a) {
; CHECK-LABEL: test_redor_v16i1:
; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[5]
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[6]
; CHECK-NEXT: orr w8, w8, w11
; CHECK-NEXT: umov w11, v0.b[7]
; CHECK-NEXT: orr w8, w8, w12
; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: orr w8, w8, w11
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v16i1:
; GISEL: // %bb.0:
; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2]
; GISEL-NEXT: mov b3, v0.b[3]
; GISEL-NEXT: mov b4, v0.b[4]
; GISEL-NEXT: mov b5, v0.b[5]
; GISEL-NEXT: mov b6, v0.b[6]
; GISEL-NEXT: mov b7, v0.b[7]
; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: fmov w10, s2
; GISEL-NEXT: fmov w11, s3
; GISEL-NEXT: mov b16, v0.b[8]
; GISEL-NEXT: mov b17, v0.b[9]
; GISEL-NEXT: mov b18, v0.b[10]
; GISEL-NEXT: mov b19, v0.b[11]
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: orr w9, w10, w11
; GISEL-NEXT: fmov w10, s4
; GISEL-NEXT: fmov w11, s5
; GISEL-NEXT: fmov w12, s6
; GISEL-NEXT: fmov w13, s7
; GISEL-NEXT: mov b20, v0.b[12]
; GISEL-NEXT: mov b21, v0.b[13]
; GISEL-NEXT: mov b22, v0.b[14]
; GISEL-NEXT: mov b23, v0.b[15]
; GISEL-NEXT: orr w10, w10, w11
; GISEL-NEXT: orr w11, w12, w13
; GISEL-NEXT: fmov w12, s16
; GISEL-NEXT: fmov w13, s17
; GISEL-NEXT: fmov w14, s18
; GISEL-NEXT: fmov w15, s19
; GISEL-NEXT: fmov w16, s22
; GISEL-NEXT: fmov w17, s23
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: orr w12, w12, w13
; GISEL-NEXT: orr w9, w10, w11
; GISEL-NEXT: orr w13, w14, w15
; GISEL-NEXT: fmov w14, s20
; GISEL-NEXT: fmov w15, s21
; GISEL-NEXT: orr w10, w12, w13
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: orr w14, w14, w15
; GISEL-NEXT: orr w15, w16, w17
; GISEL-NEXT: orr w11, w14, w15
; GISEL-NEXT: orr w9, w10, w11
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: and w0, w8, #0x1
; GISEL-NEXT: ret
%or_result = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %a)
ret i1 %or_result
}
define i8 @test_redor_v1i8(<1 x i8> %a) {
; CHECK-LABEL: test_redor_v1i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w0, v0.b[0]
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v1i8:
; GISEL: // %bb.0:
; GISEL-NEXT: fmov x0, d0
; GISEL-NEXT: // kill: def $w0 killed $w0 killed $x0
; GISEL-NEXT: ret
%or_result = call i8 @llvm.vector.reduce.or.v1i8(<1 x i8> %a)
ret i8 %or_result
}
define i8 @test_redor_v3i8(<3 x i8> %a) {
; CHECK-LABEL: test_redor_v3i8:
; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, w0, w1
; CHECK-NEXT: orr w0, w8, w2
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v3i8:
; GISEL: // %bb.0:
; GISEL-NEXT: orr w8, w0, w1
; GISEL-NEXT: orr w0, w8, w2
; GISEL-NEXT: ret
%or_result = call i8 @llvm.vector.reduce.or.v3i8(<3 x i8> %a)
ret i8 %or_result
}
define i8 @test_redor_v4i8(<4 x i8> %a) {
; CHECK-LABEL: test_redor_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: umov w9, v0.h[0]
; CHECK-NEXT: umov w10, v0.h[2]
; CHECK-NEXT: umov w11, v0.h[3]
; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: orr w0, w8, w11
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v4i8:
; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov h1, v0.h[1]
; GISEL-NEXT: mov h2, v0.h[2]
; GISEL-NEXT: mov h3, v0.h[3]
; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: fmov w10, s2
; GISEL-NEXT: fmov w11, s3
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: orr w9, w10, w11
; GISEL-NEXT: orr w0, w8, w9
; GISEL-NEXT: ret
%or_result = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> %a)
ret i8 %or_result
}
define i8 @test_redor_v8i8(<8 x i8> %a) {
; CHECK-LABEL: test_redor_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: umov w13, v0.b[5]
; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[6]
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[7]
; CHECK-NEXT: orr w8, w8, w11
; CHECK-NEXT: orr w8, w8, w12
; CHECK-NEXT: orr w8, w8, w13
; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: orr w0, w8, w10
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v8i8:
; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2]
; GISEL-NEXT: mov b3, v0.b[3]
; GISEL-NEXT: mov b4, v0.b[4]
; GISEL-NEXT: mov b5, v0.b[5]
; GISEL-NEXT: mov b6, v0.b[6]
; GISEL-NEXT: mov b7, v0.b[7]
; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: fmov w10, s2
; GISEL-NEXT: fmov w11, s3
; GISEL-NEXT: fmov w12, s4
; GISEL-NEXT: fmov w13, s5
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: fmov w9, s6
; GISEL-NEXT: orr w10, w10, w11
; GISEL-NEXT: fmov w11, s7
; GISEL-NEXT: orr w12, w12, w13
; GISEL-NEXT: orr w8, w8, w10
; GISEL-NEXT: orr w9, w9, w11
; GISEL-NEXT: orr w9, w12, w9
; GISEL-NEXT: orr w0, w8, w9
; GISEL-NEXT: ret
%or_result = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %a)
ret i8 %or_result
}
define i8 @test_redor_v16i8(<16 x i8> %a) {
; CHECK-LABEL: test_redor_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[5]
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[6]
; CHECK-NEXT: orr w8, w8, w11
; CHECK-NEXT: umov w11, v0.b[7]
; CHECK-NEXT: orr w8, w8, w12
; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: orr w0, w8, w11
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v16i8:
; GISEL: // %bb.0:
; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2]
; GISEL-NEXT: mov b3, v0.b[3]
; GISEL-NEXT: mov b4, v0.b[4]
; GISEL-NEXT: mov b5, v0.b[5]
; GISEL-NEXT: mov b6, v0.b[6]
; GISEL-NEXT: mov b7, v0.b[7]
; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: fmov w10, s2
; GISEL-NEXT: fmov w11, s3
; GISEL-NEXT: fmov w12, s4
; GISEL-NEXT: fmov w13, s5
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: fmov w9, s6
; GISEL-NEXT: orr w10, w10, w11
; GISEL-NEXT: fmov w11, s7
; GISEL-NEXT: orr w12, w12, w13
; GISEL-NEXT: orr w8, w8, w10
; GISEL-NEXT: orr w9, w9, w11
; GISEL-NEXT: orr w9, w12, w9
; GISEL-NEXT: orr w0, w8, w9
; GISEL-NEXT: ret
%or_result = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %a)
ret i8 %or_result
}
define i8 @test_redor_v32i8(<32 x i8> %a) {
; CHECK-LABEL: test_redor_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: umov w9, v0.b[0]
; CHECK-NEXT: umov w10, v0.b[2]
; CHECK-NEXT: umov w11, v0.b[3]
; CHECK-NEXT: umov w12, v0.b[4]
; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: umov w9, v0.b[5]
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: umov w10, v0.b[6]
; CHECK-NEXT: orr w8, w8, w11
; CHECK-NEXT: umov w11, v0.b[7]
; CHECK-NEXT: orr w8, w8, w12
; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: orr w0, w8, w11
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v32i8:
; GISEL: // %bb.0:
; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b
; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov b1, v0.b[1]
; GISEL-NEXT: mov b2, v0.b[2]
; GISEL-NEXT: mov b3, v0.b[3]
; GISEL-NEXT: mov b4, v0.b[4]
; GISEL-NEXT: mov b5, v0.b[5]
; GISEL-NEXT: mov b6, v0.b[6]
; GISEL-NEXT: mov b7, v0.b[7]
; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: fmov w10, s2
; GISEL-NEXT: fmov w11, s3
; GISEL-NEXT: fmov w12, s4
; GISEL-NEXT: fmov w13, s5
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: fmov w9, s6
; GISEL-NEXT: orr w10, w10, w11
; GISEL-NEXT: fmov w11, s7
; GISEL-NEXT: orr w12, w12, w13
; GISEL-NEXT: orr w8, w8, w10
; GISEL-NEXT: orr w9, w9, w11
; GISEL-NEXT: orr w9, w12, w9
; GISEL-NEXT: orr w0, w8, w9
; GISEL-NEXT: ret
%or_result = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %a)
ret i8 %or_result
}
define i16 @test_redor_v4i16(<4 x i16> %a) {
; CHECK-LABEL: test_redor_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: umov w9, v0.h[0]
; CHECK-NEXT: umov w10, v0.h[2]
; CHECK-NEXT: umov w11, v0.h[3]
; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: orr w0, w8, w11
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v4i16:
; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov h1, v0.h[1]
; GISEL-NEXT: mov h2, v0.h[2]
; GISEL-NEXT: mov h3, v0.h[3]
; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: fmov w10, s2
; GISEL-NEXT: fmov w11, s3
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: orr w9, w10, w11
; GISEL-NEXT: orr w0, w8, w9
; GISEL-NEXT: ret
%or_result = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %a)
ret i16 %or_result
}
define i16 @test_redor_v8i16(<8 x i16> %a) {
; CHECK-LABEL: test_redor_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: umov w9, v0.h[0]
; CHECK-NEXT: umov w10, v0.h[2]
; CHECK-NEXT: umov w11, v0.h[3]
; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: orr w0, w8, w11
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v8i16:
; GISEL: // %bb.0:
; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov h1, v0.h[1]
; GISEL-NEXT: mov h2, v0.h[2]
; GISEL-NEXT: mov h3, v0.h[3]
; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: fmov w10, s2
; GISEL-NEXT: fmov w11, s3
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: orr w9, w10, w11
; GISEL-NEXT: orr w0, w8, w9
; GISEL-NEXT: ret
%or_result = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %a)
ret i16 %or_result
}
define i16 @test_redor_v16i16(<16 x i16> %a) {
; CHECK-LABEL: test_redor_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: umov w9, v0.h[0]
; CHECK-NEXT: umov w10, v0.h[2]
; CHECK-NEXT: umov w11, v0.h[3]
; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: orr w8, w8, w10
; CHECK-NEXT: orr w0, w8, w11
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v16i16:
; GISEL: // %bb.0:
; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b
; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov h1, v0.h[1]
; GISEL-NEXT: mov h2, v0.h[2]
; GISEL-NEXT: mov h3, v0.h[3]
; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: fmov w10, s2
; GISEL-NEXT: fmov w11, s3
; GISEL-NEXT: orr w8, w8, w9
; GISEL-NEXT: orr w9, w10, w11
; GISEL-NEXT: orr w0, w8, w9
; GISEL-NEXT: ret
%or_result = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %a)
ret i16 %or_result
}
define i32 @test_redor_v2i32(<2 x i32> %a) {
; CHECK-LABEL: test_redor_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: orr w0, w9, w8
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v2i32:
; GISEL: // %bb.0:
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov s1, v0.s[1]
; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: orr w0, w8, w9
; GISEL-NEXT: ret
%or_result = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %a)
ret i32 %or_result
}
define i32 @test_redor_v4i32(<4 x i32> %a) {
; CHECK-LABEL: test_redor_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: orr w0, w9, w8
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v4i32:
; GISEL: // %bb.0:
; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov s1, v0.s[1]
; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: orr w0, w8, w9
; GISEL-NEXT: ret
%or_result = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %a)
ret i32 %or_result
}
define i32 @test_redor_v8i32(<8 x i32> %a) {
; CHECK-LABEL: test_redor_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: orr w0, w9, w8
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v8i32:
; GISEL: // %bb.0:
; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b
; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: orr v0.8b, v0.8b, v1.8b
; GISEL-NEXT: mov s1, v0.s[1]
; GISEL-NEXT: fmov w8, s0
; GISEL-NEXT: fmov w9, s1
; GISEL-NEXT: orr w0, w8, w9
; GISEL-NEXT: ret
%or_result = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %a)
ret i32 %or_result
}
define i64 @test_redor_v2i64(<2 x i64> %a) {
; CHECK-LABEL: test_redor_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v2i64:
; GISEL: // %bb.0:
; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: fmov x8, d0
; GISEL-NEXT: fmov x9, d1
; GISEL-NEXT: orr x0, x8, x9
; GISEL-NEXT: ret
%or_result = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %a)
ret i64 %or_result
}
define i64 @test_redor_v4i64(<4 x i64> %a) {
; CHECK-LABEL: test_redor_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret
;
; GISEL-LABEL: test_redor_v4i64:
; GISEL: // %bb.0:
; GISEL-NEXT: orr v0.16b, v0.16b, v1.16b
; GISEL-NEXT: mov d1, v0.d[1]
; GISEL-NEXT: fmov x8, d0
; GISEL-NEXT: fmov x9, d1
; GISEL-NEXT: orr x0, x8, x9
; GISEL-NEXT: ret
%or_result = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %a)
ret i64 %or_result
}
declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1>)
declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>)
declare i1 @llvm.vector.reduce.or.v8i1(<8 x i1>)
declare i1 @llvm.vector.reduce.or.v16i1(<16 x i1>)
declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)
declare i64 @llvm.vector.reduce.or.v4i64(<4 x i64>)
declare i32 @llvm.vector.reduce.or.v2i32(<2 x i32>)
declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)
declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32>)
declare i16 @llvm.vector.reduce.or.v4i16(<4 x i16>)
declare i16 @llvm.vector.reduce.or.v8i16(<8 x i16>)
declare i16 @llvm.vector.reduce.or.v16i16(<16 x i16>)
declare i8 @llvm.vector.reduce.or.v1i8(<1 x i8>)
declare i8 @llvm.vector.reduce.or.v3i8(<3 x i8>)
declare i8 @llvm.vector.reduce.or.v4i8(<4 x i8>)
declare i8 @llvm.vector.reduce.or.v8i8(<8 x i8>)
declare i8 @llvm.vector.reduce.or.v16i8(<16 x i8>)
declare i8 @llvm.vector.reduce.or.v32i8(<32 x i8>)
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