528ee161c9
There are no patterns for the AArch64ISD::BSP ISD node for anything other than NEON vectors at the moment. As a result, if we hit these combines for vectors wider than a NEON vector (such as what we might get with fixed length SVE) we will fail to lower. This patch simply prevents us from attempting the combines if the input vector type is too wide. Reviewed By: peterwaller-arm Differential Revision: https://reviews.llvm.org/D100961
30 lines
1.1 KiB
LLVM
30 lines
1.1 KiB
LLVM
; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s
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target triple = "aarch64"
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;
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; NOTE: SVE lowering for the BSP pseudoinst is not currently implemented, so we
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; don't currently expect the code below to lower to BSL/BIT/BIF. Once
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; this is implemented, this test will be fleshed out.
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;
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define <8 x i32> @fixed_bitselect_v8i32(<8 x i32>* %pre_cond_ptr, <8 x i32>* %left_ptr, <8 x i32>* %right_ptr) #0 {
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; CHECK-LABEL: fixed_bitselect_v8i32:
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; CHECK-NOT: bsl {{.*}}, {{.*}}, {{.*}}
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; CHECK-NOT: bit {{.*}}, {{.*}}, {{.*}}
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; CHECK-NOT: bif {{.*}}, {{.*}}, {{.*}}
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; CHECK: ret
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%pre_cond = load <8 x i32>, <8 x i32>* %pre_cond_ptr
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%left = load <8 x i32>, <8 x i32>* %left_ptr
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%right = load <8 x i32>, <8 x i32>* %right_ptr
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%neg_cond = sub <8 x i32> zeroinitializer, %pre_cond
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%min_cond = add <8 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
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%left_bits_0 = and <8 x i32> %neg_cond, %left
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%right_bits_0 = and <8 x i32> %min_cond, %right
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%bsl0000 = or <8 x i32> %right_bits_0, %left_bits_0
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ret <8 x i32> %bsl0000
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}
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attributes #0 = { "target-features"="+sve" }
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