adec922361
We would like to start pushing -mcpu=generic towards enabling the set of features that improves performance for some CPUs, without hurting any others. A blend of the performance options hopefully beneficial to all CPUs. The largest part of that is enabling in-order scheduling using the Cortex-A55 schedule model. This is similar to the Arm backend change from eecb353d0e25ba which made -mcpu=generic perform in-order scheduling using the cortex-a8 schedule model. The idea is that in-order cpu's require the most help in instruction scheduling, whereas out-of-order cpus can for the most part out-of-order schedule around different codegen. Our benchmarking suggests that hypothesis holds. When running on an in-order core this improved performance by 3.8% geomean on a set of DSP workloads, 2% geomean on some other embedded benchmark and between 1% and 1.8% on a set of singlecore and multicore workloads, all running on a Cortex-A55 cluster. On an out-of-order cpu the results are a lot more noisy but show flat performance or an improvement. On the set of DSP and embedded benchmarks, run on a Cortex-A78 there was a very noisy 1% speed improvement. Using the most detailed results I could find, SPEC2006 runs on a Neoverse N1 show a small increase in instruction count (+0.127%), but a decrease in cycle counts (-0.155%, on average). The instruction count is very low noise, the cycle count is more noisy with a 0.15% decrease not being significant. SPEC2k17 shows a small decrease (-0.2%) in instruction count leading to a -0.296% decrease in cycle count. These results are within noise margins but tend to show a small improvement in general. When specifying an Apple target, clang will set "-target-cpu apple-a7" on the command line, so should not be affected by this change when running from clang. This also doesn't enable more runtime unrolling like -mcpu=cortex-a55 does, only changing the schedule used. A lot of existing tests have updated. This is a summary of the important differences: - Most changes are the same instructions in a different order. - Sometimes this leads to very minor inefficiencies, such as requiring an extra mov to move variables into r0/v0 for the return value of a test function. - misched-fusion.ll was no longer fusing the pairs of instructions it should, as per D110561. I've changed the schedule used in the test for now. - neon-mla-mls.ll now uses "mul; sub" as opposed to "neg; mla" due to the different latencies. This seems fine to me. - Some SVE tests do not always remove movprfx where they did before due to different register allocation giving different destructive forms. - The tests argument-blocks-array-of-struct.ll and arm64-windows-calls.ll produce two LDR where they previously produced an LDP due to store-pair-suppress kicking in. - arm64-ldp.ll and arm64-neon-copy.ll are missing pre/postinc on LPD. - Some tests such as arm64-neon-mul-div.ll and ragreedy-local-interval-cost.ll have more, less or just different spilling. - In aarch64_generated_funcs.ll.generated.expected one part of the function is no longer outlined. Interestingly if I switch this to use any other scheduled even less is outlined. Some of these are expected to happen, such as differences in outlining or register spilling. There will be places where these result in worse codegen, places where they are better, with the SPEC instruction counts suggesting it is not a decrease overall, on average. Differential Revision: https://reviews.llvm.org/D110830
175 lines
4.7 KiB
LLVM
175 lines
4.7 KiB
LLVM
; RUN: llc -mtriple=arm64-apple-ios15 %s -o - | FileCheck %s --check-prefixes=CHECK-NOAUTH,CHECK
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; RUN: llc -mtriple=arm64-apple-ios15 -mcpu=apple-a13 %s -o - | FileCheck %s --check-prefixes=CHECK-NOAUTH,CHECK
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; RUN: llc -mtriple=arm64e-apple-ios15 %s -o - | FileCheck %s --check-prefixes=CHECK-AUTH,CHECK
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; Important details in prologue:
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; * x22 is stored just below x29
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; * Enough stack space is allocated for everything
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define swifttailcc void @simple(i8* swiftasync %ctx) "frame-pointer"="all" {
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; CHECK-LABEL: simple:
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; CHECK: orr x29, x29, #0x100000000000000
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; CHECK: sub sp, sp, #32
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; CHECK: stp x29, x30, [sp, #16]
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; CHECK-NOAUTH-DAG: str x22, [sp, #8]
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; CHECK-AUTH: add x16, sp, #8
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; CHECK-AUTH: movk x16, #49946, lsl #48
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; CHECK-AUTH: mov x17, x22
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; CHECK-AUTH: pacdb x17, x16
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; CHECK-AUTH: str x17, [sp, #8]
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; CHECK-DAG: add x29, sp, #16
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; CHECK: .cfi_def_cfa w29, 16
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; CHECK: .cfi_offset w30, -8
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; CHECK: .cfi_offset w29, -16
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;[...]
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; CHECK: ldp x29, x30, [sp, #16]
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; CHECK: and x29, x29, #0xefffffffffffffff
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; CHECK: add sp, sp, #32
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ret void
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}
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define swifttailcc void @more_csrs(i8* swiftasync %ctx) "frame-pointer"="all" {
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; CHECK-LABEL: more_csrs:
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; CHECK: orr x29, x29, #0x100000000000000
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; CHECK: str x23, [sp, #-32]!
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; CHECK: stp x29, x30, [sp, #16]
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; CHECK-NOAUTH-DAG: str x22, [sp, #8]
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; CHECK-AUTH: add x16, sp, #8
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; CHECK-AUTH: movk x16, #49946, lsl #48
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; CHECK-AUTH: mov x17, x22
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; CHECK-AUTH: pacdb x17, x16
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; CHECK-AUTH: str x17, [sp, #8]
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; CHECK-DAG: add x29, sp, #16
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; CHECK: .cfi_def_cfa w29, 16
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; CHECK: .cfi_offset w30, -8
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; CHECK: .cfi_offset w29, -16
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; CHECK: .cfi_offset w23, -32
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; [...]
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; CHECK: ldp x29, x30, [sp, #16]
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; CHECK: ldr x23, [sp], #32
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; CHECK: and x29, x29, #0xefffffffffffffff
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call void asm sideeffect "", "~{x23}"()
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ret void
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}
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define swifttailcc void @locals(i8* swiftasync %ctx) "frame-pointer"="all" {
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; CHECK-LABEL: locals:
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; CHECK: orr x29, x29, #0x100000000000000
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; CHECK: sub sp, sp, #64
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; CHECK: stp x29, x30, [sp, #48]
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; CHECK-NOAUTH-DAG: str x22, [sp, #40]
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; CHECK-AUTH: add x16, sp, #40
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; CHECK-AUTH: movk x16, #49946, lsl #48
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; CHECK-AUTH: mov x17, x22
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; CHECK-AUTH: pacdb x17, x16
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; CHECK-AUTH: str x17, [sp, #40]
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; CHECK-DAG: add x29, sp, #48
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; CHECK: .cfi_def_cfa w29, 16
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; CHECK: .cfi_offset w30, -8
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; CHECK: .cfi_offset w29, -16
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; CHECK: mov x0, sp
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; CHECK: bl _bar
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; [...]
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; CHECK: ldp x29, x30, [sp, #48]
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; CHECK: and x29, x29, #0xefffffffffffffff
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; CHECK: add sp, sp, #64
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%var = alloca i32, i32 10
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call void @bar(i32* %var)
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ret void
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}
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define swifttailcc void @use_input_context(i8* swiftasync %ctx, i8** %ptr) "frame-pointer"="all" {
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; CHECK-LABEL: use_input_context:
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; CHECK-NOAUTH: str x22, [sp
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; CHECK-AUTH: mov x17, x22
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; CHECK-NOT: x22
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; CHECK: str x22, [x0]
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store i8* %ctx, i8** %ptr
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ret void
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}
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define swifttailcc i8** @context_in_func() "frame-pointer"="non-leaf" {
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; CHECK-LABEL: context_in_func:
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; CHECK-NOAUTH: str xzr, [sp, #8]
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; CHECK-AUTH: add x16, sp, #8
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; CHECK-AUTH: movk x16, #49946, lsl #48
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; CHECK-AUTH: mov x17, xzr
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; CHECK-AUTH: pacdb x17, x16
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; CHECK-AUTH: str x17, [sp, #8]
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%ptr = call i8** @llvm.swift.async.context.addr()
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ret i8** %ptr
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}
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define swifttailcc void @write_frame_context(i8* swiftasync %ctx, i8* %newctx) "frame-pointer"="non-leaf" {
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; CHECK-LABEL: write_frame_context:
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; CHECK: sub x[[ADDR:[0-9]+]], x29, #8
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; CHECK: str x0, [x[[ADDR]]]
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%ptr = call i8** @llvm.swift.async.context.addr()
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store i8* %newctx, i8** %ptr
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ret void
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}
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define swifttailcc void @simple_fp_elim(i8* swiftasync %ctx) "frame-pointer"="non-leaf" {
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; CHECK-LABEL: simple_fp_elim:
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; CHECK-NOT: orr x29, x29, #0x100000000000000
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ret void
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}
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define swifttailcc void @large_frame(i8* swiftasync %ctx) "frame-pointer"="all" {
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; CHECK-LABEL: large_frame:
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; CHECK: str x28, [sp, #-32]!
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; CHECK: stp x29, x30, [sp, #16]
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; CHECK-NOAUTH-DAG: str x22, [sp, #8]
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; CHECK-DAG: add x29, sp, #16
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; CHECK: sub sp, sp, #1024
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; [...]
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; CHECK: add sp, sp, #1024
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; CHECK: ldp x29, x30, [sp, #16]
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; CHECK: ldr x28, [sp], #32
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; CHECK: ret
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%var = alloca i8, i32 1024
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ret void
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}
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; Important point is that there is just one 8-byte gap in the CSR region (right
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; now just above d8) to realign the stack.
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define swifttailcc void @two_unpaired_csrs(i8* swiftasync) "frame-pointer"="all" {
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; CHECK-LABEL: two_unpaired_csrs:
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; CHECK: str d8, [sp, #-48]!
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; CHECK: str x19, [sp, #16]
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; CHECK: stp x29, x30, [sp, #32]
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; CHECK-NOAUTH-DAG: str x22, [sp, #24]
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; CHECK-DAG: add x29, sp, #32
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; CHECK: .cfi_def_cfa w29, 16
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; CHECK: .cfi_offset w30, -8
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; CHECK: .cfi_offset w29, -16
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; CHECK: .cfi_offset w19, -32
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; CHECK: .cfi_offset b8, -48
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call void asm "","~{x19},~{d8}"()
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call swifttailcc void @bar(i32* undef)
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ret void
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}
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declare swifttailcc void @bar(i32*)
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declare i8** @llvm.swift.async.context.addr()
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