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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
Venkata Ramanaiah Nalamothu 04fff547e2 [AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range 
Currently the return address ABI registers s[30:31], which fall in the call
clobbered register range, are added as a live-in on the function entry to
preserve its value when we have calls so that it gets saved and restored
around the calls.

But the DWARF unwind information (CFI) needs to track where the return address
resides in a frame and the above approach makes it difficult to track the
return address when the CFI information is emitted during the frame lowering,
due to the involvment of understanding the control flow.

This patch moves the return address ABI registers s[30:31] into callee saved
registers range and stops adding live-in for return address registers, so that
the CFI machinery will know where the return address resides when CSR
save/restore happen during the frame lowering.

And doing the above poses an issue that now the return instruction uses undefined
register `sgpr30_sgpr31`. This is resolved by hiding the return address register
use by the return instruction through the `SI_RETURN` pseudo instruction, which
doesn't take any input operands, until the `SI_RETURN` pseudo gets lowered to the
`S_SETPC_B64_return` during the `expandPostRAPseudo()`.

As an added benefit, this patch simplifies overall return instruction handling.

Note: The AMDGPU CFI changes are there only in the downstream code and another
version of this patch will be posted for review for the downstream code.

Reviewed By: arsenm, ronlieb

Differential Revision: https://reviews.llvm.org/D114652
2022-03-09 12:18:02 +05:30

1804 lines
62 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s
define i8 @v_lshr_i8(i8 %value, i8 %amount) {
; GFX6-LABEL: v_lshr_i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_lshr_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_lshr_i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-NEXT: v_lshrrev_b16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr i8 %value, %amount
ret i8 %result
}
define i8 @v_lshr_i8_7(i8 %value) {
; GFX6-LABEL: v_lshr_i8_7:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_bfe_u32 v0, v0, 7, 1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_lshr_i8_7:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, 7
; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_lshr_i8_7:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, 7
; GFX9-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i8_7:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10-NEXT: v_lshrrev_b16 v0, 7, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr i8 %value, 7
ret i8 %result
}
define amdgpu_ps i8 @s_lshr_i8(i8 inreg %value, i8 inreg %amount) {
; GCN-LABEL: s_lshr_i8:
; GCN: ; %bb.0:
; GCN-NEXT: s_and_b32 s0, s0, 0xff
; GCN-NEXT: s_lshr_b32 s0, s0, s1
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s0, s0, 0xff
; GFX10-NEXT: s_lshr_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i8 %value, %amount
ret i8 %result
}
define amdgpu_ps i8 @s_lshr_i8_7(i8 inreg %value) {
; GCN-LABEL: s_lshr_i8_7:
; GCN: ; %bb.0:
; GCN-NEXT: s_bfe_u32 s0, s0, 0x10007
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_i8_7:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_bfe_u32 s0, s0, 0x10007
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i8 %value, 7
ret i8 %result
}
define i24 @v_lshr_i24(i24 %value, i24 %amount) {
; GCN-LABEL: v_lshr_i24:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s4, 0xffffff
; GCN-NEXT: v_and_b32_e32 v1, s4, v1
; GCN-NEXT: v_and_b32_e32 v0, s4, v0
; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 0xffffff
; GFX10-NEXT: v_and_b32_e32 v1, s4, v1
; GFX10-NEXT: v_and_b32_e32 v0, s4, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr i24 %value, %amount
ret i24 %result
}
define i24 @v_lshr_i24_7(i24 %value) {
; GCN-LABEL: v_lshr_i24_7:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_bfe_u32 v0, v0, 7, 17
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i24_7:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_bfe_u32 v0, v0, 7, 17
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr i24 %value, 7
ret i24 %result
}
define amdgpu_ps i24 @s_lshr_i24(i24 inreg %value, i24 inreg %amount) {
; GCN-LABEL: s_lshr_i24:
; GCN: ; %bb.0:
; GCN-NEXT: s_and_b32 s0, s0, 0xffffff
; GCN-NEXT: s_lshr_b32 s0, s0, s1
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s0, s0, 0xffffff
; GFX10-NEXT: s_lshr_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i24 %value, %amount
ret i24 %result
}
define amdgpu_ps i24 @s_lshr_i24_7(i24 inreg %value) {
; GCN-LABEL: s_lshr_i24_7:
; GCN: ; %bb.0:
; GCN-NEXT: s_bfe_u32 s0, s0, 0x110007
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_i24_7:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_bfe_u32 s0, s0, 0x110007
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i24 %value, 7
ret i24 %result
}
define i32 @v_lshr_i32(i32 %value, i32 %amount) {
; GCN-LABEL: v_lshr_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr i32 %value, %amount
ret i32 %result
}
define i32 @v_lshr_i32_31(i32 %value) {
; GCN-LABEL: v_lshr_i32_31:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i32_31:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 31, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr i32 %value, 31
ret i32 %result
}
define amdgpu_ps i32 @s_lshr_i32(i32 inreg %value, i32 inreg %amount) {
; GCN-LABEL: s_lshr_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_lshr_b32 s0, s0, s1
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i32 %value, %amount
ret i32 %result
}
define amdgpu_ps i32 @s_lshr_i32_31(i32 inreg %value) {
; GCN-LABEL: s_lshr_i32_31:
; GCN: ; %bb.0:
; GCN-NEXT: s_lshr_b32 s0, s0, 31
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_i32_31:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s0, s0, 31
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i32 %value, 31
ret i32 %result
}
define amdgpu_ps float @lshr_i32_sv(i32 inreg %value, i32 %amount) {
; GFX6-LABEL: lshr_i32_sv:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: lshr_i32_sv:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: lshr_i32_sv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: lshr_i32_sv:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshrrev_b32_e64 v0, v0, s0
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i32 %value, %amount
%cast = bitcast i32 %result to float
ret float %cast
}
define amdgpu_ps float @lshr_i32_vs(i32 %value, i32 inreg %amount) {
; GCN-LABEL: lshr_i32_vs:
; GCN: ; %bb.0:
; GCN-NEXT: v_lshrrev_b32_e32 v0, s0, v0
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: lshr_i32_vs:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshrrev_b32_e32 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i32 %value, %amount
%cast = bitcast i32 %result to float
ret float %cast
}
define <2 x i32> @v_lshr_v2i32(<2 x i32> %value, <2 x i32> %amount) {
; GCN-LABEL: v_lshr_v2i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v0, v2, v0
; GCN-NEXT: v_lshrrev_b32_e32 v1, v3, v1
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_v2i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v0, v2, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v1, v3, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr <2 x i32> %value, %amount
ret <2 x i32> %result
}
define <2 x i32> @v_lshr_v2i32_31(<2 x i32> %value) {
; GCN-LABEL: v_lshr_v2i32_31:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v0
; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v1
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_v2i32_31:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 31, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 31, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr <2 x i32> %value, <i32 31, i32 31>
ret <2 x i32> %result
}
define amdgpu_ps <2 x i32> @s_lshr_v2i32(<2 x i32> inreg %value, <2 x i32> inreg %amount) {
; GCN-LABEL: s_lshr_v2i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_lshr_b32 s0, s0, s2
; GCN-NEXT: s_lshr_b32 s1, s1, s3
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_v2i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s0, s0, s2
; GFX10-NEXT: s_lshr_b32 s1, s1, s3
; GFX10-NEXT: ; return to shader part epilog
%result = lshr <2 x i32> %value, %amount
ret <2 x i32> %result
}
define <3 x i32> @v_lshr_v3i32(<3 x i32> %value, <3 x i32> %amount) {
; GCN-LABEL: v_lshr_v3i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v0, v3, v0
; GCN-NEXT: v_lshrrev_b32_e32 v1, v4, v1
; GCN-NEXT: v_lshrrev_b32_e32 v2, v5, v2
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_v3i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v0, v3, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v1, v4, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v2, v5, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr <3 x i32> %value, %amount
ret <3 x i32> %result
}
define amdgpu_ps <3 x i32> @s_lshr_v3i32(<3 x i32> inreg %value, <3 x i32> inreg %amount) {
; GCN-LABEL: s_lshr_v3i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_lshr_b32 s0, s0, s3
; GCN-NEXT: s_lshr_b32 s1, s1, s4
; GCN-NEXT: s_lshr_b32 s2, s2, s5
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_v3i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s0, s0, s3
; GFX10-NEXT: s_lshr_b32 s1, s1, s4
; GFX10-NEXT: s_lshr_b32 s2, s2, s5
; GFX10-NEXT: ; return to shader part epilog
%result = lshr <3 x i32> %value, %amount
ret <3 x i32> %result
}
define <4 x i32> @v_lshr_v4i32(<4 x i32> %value, <4 x i32> %amount) {
; GCN-LABEL: v_lshr_v4i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v0, v4, v0
; GCN-NEXT: v_lshrrev_b32_e32 v1, v5, v1
; GCN-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GCN-NEXT: v_lshrrev_b32_e32 v3, v7, v3
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_v4i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v0, v4, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v1, v5, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v3, v7, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr <4 x i32> %value, %amount
ret <4 x i32> %result
}
define amdgpu_ps <4 x i32> @s_lshr_v4i32(<4 x i32> inreg %value, <4 x i32> inreg %amount) {
; GCN-LABEL: s_lshr_v4i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_lshr_b32 s0, s0, s4
; GCN-NEXT: s_lshr_b32 s1, s1, s5
; GCN-NEXT: s_lshr_b32 s2, s2, s6
; GCN-NEXT: s_lshr_b32 s3, s3, s7
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_v4i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s0, s0, s4
; GFX10-NEXT: s_lshr_b32 s1, s1, s5
; GFX10-NEXT: s_lshr_b32 s2, s2, s6
; GFX10-NEXT: s_lshr_b32 s3, s3, s7
; GFX10-NEXT: ; return to shader part epilog
%result = lshr <4 x i32> %value, %amount
ret <4 x i32> %result
}
define <5 x i32> @v_lshr_v5i32(<5 x i32> %value, <5 x i32> %amount) {
; GCN-LABEL: v_lshr_v5i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v0, v5, v0
; GCN-NEXT: v_lshrrev_b32_e32 v1, v6, v1
; GCN-NEXT: v_lshrrev_b32_e32 v2, v7, v2
; GCN-NEXT: v_lshrrev_b32_e32 v3, v8, v3
; GCN-NEXT: v_lshrrev_b32_e32 v4, v9, v4
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_v5i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v0, v5, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v1, v6, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v2, v7, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v3, v8, v3
; GFX10-NEXT: v_lshrrev_b32_e32 v4, v9, v4
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr <5 x i32> %value, %amount
ret <5 x i32> %result
}
define amdgpu_ps <5 x i32> @s_lshr_v5i32(<5 x i32> inreg %value, <5 x i32> inreg %amount) {
; GCN-LABEL: s_lshr_v5i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_lshr_b32 s0, s0, s5
; GCN-NEXT: s_lshr_b32 s1, s1, s6
; GCN-NEXT: s_lshr_b32 s2, s2, s7
; GCN-NEXT: s_lshr_b32 s3, s3, s8
; GCN-NEXT: s_lshr_b32 s4, s4, s9
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_v5i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s0, s0, s5
; GFX10-NEXT: s_lshr_b32 s1, s1, s6
; GFX10-NEXT: s_lshr_b32 s2, s2, s7
; GFX10-NEXT: s_lshr_b32 s3, s3, s8
; GFX10-NEXT: s_lshr_b32 s4, s4, s9
; GFX10-NEXT: ; return to shader part epilog
%result = lshr <5 x i32> %value, %amount
ret <5 x i32> %result
}
define <16 x i32> @v_lshr_v16i32(<16 x i32> %value, <16 x i32> %amount) {
; GCN-LABEL: v_lshr_v16i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v0, v16, v0
; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32
; GCN-NEXT: v_lshrrev_b32_e32 v1, v17, v1
; GCN-NEXT: v_lshrrev_b32_e32 v2, v18, v2
; GCN-NEXT: v_lshrrev_b32_e32 v3, v19, v3
; GCN-NEXT: v_lshrrev_b32_e32 v4, v20, v4
; GCN-NEXT: v_lshrrev_b32_e32 v5, v21, v5
; GCN-NEXT: v_lshrrev_b32_e32 v6, v22, v6
; GCN-NEXT: v_lshrrev_b32_e32 v7, v23, v7
; GCN-NEXT: v_lshrrev_b32_e32 v8, v24, v8
; GCN-NEXT: v_lshrrev_b32_e32 v9, v25, v9
; GCN-NEXT: v_lshrrev_b32_e32 v10, v26, v10
; GCN-NEXT: v_lshrrev_b32_e32 v11, v27, v11
; GCN-NEXT: v_lshrrev_b32_e32 v12, v28, v12
; GCN-NEXT: v_lshrrev_b32_e32 v13, v29, v13
; GCN-NEXT: v_lshrrev_b32_e32 v14, v30, v14
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v15, v16, v15
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_v16i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: v_lshrrev_b32_e32 v0, v16, v0
; GFX10-NEXT: v_lshrrev_b32_e32 v1, v17, v1
; GFX10-NEXT: v_lshrrev_b32_e32 v2, v18, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v3, v19, v3
; GFX10-NEXT: v_lshrrev_b32_e32 v4, v20, v4
; GFX10-NEXT: v_lshrrev_b32_e32 v5, v21, v5
; GFX10-NEXT: v_lshrrev_b32_e32 v6, v22, v6
; GFX10-NEXT: v_lshrrev_b32_e32 v7, v23, v7
; GFX10-NEXT: v_lshrrev_b32_e32 v8, v24, v8
; GFX10-NEXT: v_lshrrev_b32_e32 v9, v25, v9
; GFX10-NEXT: v_lshrrev_b32_e32 v10, v26, v10
; GFX10-NEXT: v_lshrrev_b32_e32 v11, v27, v11
; GFX10-NEXT: v_lshrrev_b32_e32 v12, v28, v12
; GFX10-NEXT: v_lshrrev_b32_e32 v13, v29, v13
; GFX10-NEXT: v_lshrrev_b32_e32 v14, v30, v14
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v15, v31, v15
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr <16 x i32> %value, %amount
ret <16 x i32> %result
}
define amdgpu_ps <16 x i32> @s_lshr_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) {
; GCN-LABEL: s_lshr_v16i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_lshr_b32 s0, s0, s16
; GCN-NEXT: s_lshr_b32 s1, s1, s17
; GCN-NEXT: s_lshr_b32 s2, s2, s18
; GCN-NEXT: s_lshr_b32 s3, s3, s19
; GCN-NEXT: s_lshr_b32 s4, s4, s20
; GCN-NEXT: s_lshr_b32 s5, s5, s21
; GCN-NEXT: s_lshr_b32 s6, s6, s22
; GCN-NEXT: s_lshr_b32 s7, s7, s23
; GCN-NEXT: s_lshr_b32 s8, s8, s24
; GCN-NEXT: s_lshr_b32 s9, s9, s25
; GCN-NEXT: s_lshr_b32 s10, s10, s26
; GCN-NEXT: s_lshr_b32 s11, s11, s27
; GCN-NEXT: s_lshr_b32 s12, s12, s28
; GCN-NEXT: s_lshr_b32 s13, s13, s29
; GCN-NEXT: s_lshr_b32 s14, s14, s30
; GCN-NEXT: s_lshr_b32 s15, s15, s31
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_v16i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s0, s0, s16
; GFX10-NEXT: s_lshr_b32 s1, s1, s17
; GFX10-NEXT: s_lshr_b32 s2, s2, s18
; GFX10-NEXT: s_lshr_b32 s3, s3, s19
; GFX10-NEXT: s_lshr_b32 s4, s4, s20
; GFX10-NEXT: s_lshr_b32 s5, s5, s21
; GFX10-NEXT: s_lshr_b32 s6, s6, s22
; GFX10-NEXT: s_lshr_b32 s7, s7, s23
; GFX10-NEXT: s_lshr_b32 s8, s8, s24
; GFX10-NEXT: s_lshr_b32 s9, s9, s25
; GFX10-NEXT: s_lshr_b32 s10, s10, s26
; GFX10-NEXT: s_lshr_b32 s11, s11, s27
; GFX10-NEXT: s_lshr_b32 s12, s12, s28
; GFX10-NEXT: s_lshr_b32 s13, s13, s29
; GFX10-NEXT: s_lshr_b32 s14, s14, s30
; GFX10-NEXT: s_lshr_b32 s15, s15, s31
; GFX10-NEXT: ; return to shader part epilog
%result = lshr <16 x i32> %value, %amount
ret <16 x i32> %result
}
define i16 @v_lshr_i16(i16 %value, i16 %amount) {
; GFX6-LABEL: v_lshr_i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_lshr_i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b16_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_lshr_i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshrrev_b16_e32 v0, v1, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr i16 %value, %amount
ret i16 %result
}
define i16 @v_lshr_i16_31(i16 %value) {
; GCN-LABEL: v_lshr_i16_31:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i16_31:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr i16 %value, 31
ret i16 %result
}
define amdgpu_ps i16 @s_lshr_i16(i16 inreg %value, i16 inreg %amount) {
; GCN-LABEL: s_lshr_i16:
; GCN: ; %bb.0:
; GCN-NEXT: s_and_b32 s0, s0, 0xffff
; GCN-NEXT: s_lshr_b32 s0, s0, s1
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b32 s0, s0, 0xffff
; GFX10-NEXT: s_lshr_b32 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i16 %value, %amount
ret i16 %result
}
define amdgpu_ps i16 @s_lshr_i16_15(i16 inreg %value) {
; GCN-LABEL: s_lshr_i16_15:
; GCN: ; %bb.0:
; GCN-NEXT: s_bfe_u32 s0, s0, 0x1000f
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_i16_15:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_bfe_u32 s0, s0, 0x1000f
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i16 %value, 15
ret i16 %result
}
define amdgpu_ps half @lshr_i16_sv(i16 inreg %value, i16 %amount) {
; GFX6-LABEL: lshr_i16_sv:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s1, 0xffff
; GFX6-NEXT: v_and_b32_e32 v0, s1, v0
; GFX6-NEXT: s_and_b32 s0, s0, s1
; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: lshr_i16_sv:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_lshrrev_b16_e64 v0, v0, s0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: lshr_i16_sv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshrrev_b16_e64 v0, v0, s0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: lshr_i16_sv:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshrrev_b16 v0, v0, s0
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i16 %value, %amount
%cast = bitcast i16 %result to half
ret half %cast
}
define amdgpu_ps half @lshr_i16_vs(i16 %value, i16 inreg %amount) {
; GFX6-LABEL: lshr_i16_vs:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s1, 0xffff
; GFX6-NEXT: s_and_b32 s0, s0, s1
; GFX6-NEXT: v_and_b32_e32 v0, s1, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: lshr_i16_vs:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_lshrrev_b16_e32 v0, s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: lshr_i16_vs:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshrrev_b16_e32 v0, s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: lshr_i16_vs:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshrrev_b16 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i16 %value, %amount
%cast = bitcast i16 %result to half
ret half %cast
}
define <2 x i16> @v_lshr_v2i16(<2 x i16> %value, <2 x i16> %amount) {
; GFX6-LABEL: v_lshr_v2i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v2, v0
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v2, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_lshr_v2i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b16_e32 v2, v1, v0
; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_lshr_v2i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_pk_lshrrev_b16 v0, v1, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_v2i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_pk_lshrrev_b16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr <2 x i16> %value, %amount
ret <2 x i16> %result
}
define <2 x i16> @v_lshr_v2i16_15(<2 x i16> %value) {
; GFX6-LABEL: v_lshr_v2i16_15:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_bfe_u32 v0, v0, 15, 1
; GFX6-NEXT: v_bfe_u32 v1, v1, 15, 1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_lshr_v2i16_15:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, 15
; GFX8-NEXT: v_lshrrev_b16_e32 v1, 15, v0
; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_lshr_v2i16_15:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_pk_lshrrev_b16 v0, 15, v0 op_sel_hi:[0,1]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_v2i16_15:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_pk_lshrrev_b16 v0, 15, v0 op_sel_hi:[0,1]
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr <2 x i16> %value, <i16 15, i16 15>
ret <2 x i16> %result
}
define amdgpu_ps i32 @s_lshr_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) {
; GFX6-LABEL: s_lshr_v2i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_lshr_b32 s1, s1, s3
; GFX6-NEXT: s_lshr_b32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_lshr_v2i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_mov_b32 s3, 0xffff
; GFX8-NEXT: s_lshr_b32 s2, s0, 16
; GFX8-NEXT: s_and_b32 s0, s0, s3
; GFX8-NEXT: s_lshr_b32 s4, s1, 16
; GFX8-NEXT: s_lshr_b32 s0, s0, s1
; GFX8-NEXT: s_lshr_b32 s1, s2, s4
; GFX8-NEXT: s_lshl_b32 s1, s1, 16
; GFX8-NEXT: s_and_b32 s0, s0, s3
; GFX8-NEXT: s_or_b32 s0, s1, s0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_lshr_v2i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshr_b32 s2, s0, 16
; GFX9-NEXT: s_and_b32 s0, s0, 0xffff
; GFX9-NEXT: s_lshr_b32 s3, s1, 16
; GFX9-NEXT: s_lshr_b32 s0, s0, s1
; GFX9-NEXT: s_lshr_b32 s1, s2, s3
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_v2i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s2, s0, 16
; GFX10-NEXT: s_and_b32 s0, s0, 0xffff
; GFX10-NEXT: s_lshr_b32 s3, s1, 16
; GFX10-NEXT: s_lshr_b32 s0, s0, s1
; GFX10-NEXT: s_lshr_b32 s1, s2, s3
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1
; GFX10-NEXT: ; return to shader part epilog
%result = lshr <2 x i16> %value, %amount
%cast = bitcast <2 x i16> %result to i32
ret i32 %cast
}
define amdgpu_ps float @lshr_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {
; GFX6-LABEL: lshr_v2i16_sv:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: v_lshr_b32_e32 v0, s0, v0
; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
; GFX6-NEXT: s_and_b32 s0, s1, s2
; GFX6-NEXT: v_lshr_b32_e32 v1, s0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: lshr_v2i16_sv:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s1, s0, 16
; GFX8-NEXT: v_mov_b32_e32 v2, s1
; GFX8-NEXT: v_lshrrev_b16_e64 v1, v0, s0
; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: lshr_v2i16_sv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_pk_lshrrev_b16 v0, v0, s0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: lshr_v2i16_sv:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_pk_lshrrev_b16 v0, v0, s0
; GFX10-NEXT: ; return to shader part epilog
%result = lshr <2 x i16> %value, %amount
%cast = bitcast <2 x i16> %result to float
ret float %cast
}
define amdgpu_ps float @lshr_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) {
; GFX6-LABEL: lshr_v2i16_vs:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, s0, v0
; GFX6-NEXT: s_and_b32 s0, s1, s2
; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, s0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: lshr_v2i16_vs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s1, s0, 16
; GFX8-NEXT: v_mov_b32_e32 v2, s1
; GFX8-NEXT: v_lshrrev_b16_e32 v1, s0, v0
; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: lshr_v2i16_vs:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_pk_lshrrev_b16 v0, s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: lshr_v2i16_vs:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_pk_lshrrev_b16 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = lshr <2 x i16> %value, %amount
%cast = bitcast <2 x i16> %result to float
ret float %cast
}
; FIXME
; define <3 x i16> @v_lshr_v3i16(<3 x i16> %value, <3 x i16> %amount) {
; %result = lshr <3 x i16> %value, %amount
; ret <3 x i16> %result
; }
; define amdgpu_ps <3 x i16> @s_lshr_v3i16(<3 x i16> inreg %value, <3 x i16> inreg %amount) {
; %result = lshr <3 x i16> %value, %amount
; ret <3 x i16> %result
; }
define <2 x float> @v_lshr_v4i16(<4 x i16> %value, <4 x i16> %amount) {
; GFX6-LABEL: v_lshr_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v4, v0
; GFX6-NEXT: v_and_b32_e32 v4, s4, v5
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v4, v1
; GFX6-NEXT: v_and_b32_e32 v4, s4, v6
; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX6-NEXT: v_and_b32_e32 v4, s4, v7
; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v3, v4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_lshr_v4i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b16_e32 v4, v2, v0
; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_lshrrev_b16_e32 v2, v3, v1
; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v0, v4, v0
; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_lshr_v4i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_pk_lshrrev_b16 v0, v2, v0
; GFX9-NEXT: v_pk_lshrrev_b16 v1, v3, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_v4i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_pk_lshrrev_b16 v0, v2, v0
; GFX10-NEXT: v_pk_lshrrev_b16 v1, v3, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr <4 x i16> %value, %amount
%cast = bitcast <4 x i16> %result to <2 x float>
ret <2 x float> %cast
}
define amdgpu_ps <2 x i32> @s_lshr_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) {
; GFX6-LABEL: s_lshr_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s8, 0xffff
; GFX6-NEXT: s_and_b32 s1, s1, s8
; GFX6-NEXT: s_and_b32 s0, s0, s8
; GFX6-NEXT: s_lshr_b32 s1, s1, s5
; GFX6-NEXT: s_and_b32 s3, s3, s8
; GFX6-NEXT: s_lshr_b32 s0, s0, s4
; GFX6-NEXT: s_and_b32 s2, s2, s8
; GFX6-NEXT: s_lshr_b32 s3, s3, s7
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_lshr_b32 s2, s2, s6
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s3, 16
; GFX6-NEXT: s_or_b32 s1, s2, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_lshr_v4i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_mov_b32 s6, 0xffff
; GFX8-NEXT: s_lshr_b32 s4, s0, 16
; GFX8-NEXT: s_and_b32 s0, s0, s6
; GFX8-NEXT: s_lshr_b32 s7, s2, 16
; GFX8-NEXT: s_lshr_b32 s5, s1, 16
; GFX8-NEXT: s_and_b32 s1, s1, s6
; GFX8-NEXT: s_lshr_b32 s8, s3, 16
; GFX8-NEXT: s_lshr_b32 s0, s0, s2
; GFX8-NEXT: s_lshr_b32 s2, s4, s7
; GFX8-NEXT: s_lshr_b32 s1, s1, s3
; GFX8-NEXT: s_lshr_b32 s3, s5, s8
; GFX8-NEXT: s_lshl_b32 s2, s2, 16
; GFX8-NEXT: s_and_b32 s0, s0, s6
; GFX8-NEXT: s_or_b32 s0, s2, s0
; GFX8-NEXT: s_lshl_b32 s2, s3, 16
; GFX8-NEXT: s_and_b32 s1, s1, s6
; GFX8-NEXT: s_or_b32 s1, s2, s1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_lshr_v4i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b32 s5, 0xffff
; GFX9-NEXT: s_lshr_b32 s4, s0, 16
; GFX9-NEXT: s_and_b32 s0, s0, s5
; GFX9-NEXT: s_lshr_b32 s6, s2, 16
; GFX9-NEXT: s_lshr_b32 s0, s0, s2
; GFX9-NEXT: s_lshr_b32 s2, s4, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX9-NEXT: s_lshr_b32 s2, s1, 16
; GFX9-NEXT: s_and_b32 s1, s1, s5
; GFX9-NEXT: s_lshr_b32 s4, s3, 16
; GFX9-NEXT: s_lshr_b32 s1, s1, s3
; GFX9-NEXT: s_lshr_b32 s2, s2, s4
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_v4i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_mov_b32 s4, 0xffff
; GFX10-NEXT: s_lshr_b32 s5, s0, 16
; GFX10-NEXT: s_and_b32 s0, s0, s4
; GFX10-NEXT: s_lshr_b32 s6, s2, 16
; GFX10-NEXT: s_lshr_b32 s0, s0, s2
; GFX10-NEXT: s_lshr_b32 s2, s5, s6
; GFX10-NEXT: s_lshr_b32 s5, s1, 16
; GFX10-NEXT: s_and_b32 s1, s1, s4
; GFX10-NEXT: s_lshr_b32 s4, s3, 16
; GFX10-NEXT: s_lshr_b32 s1, s1, s3
; GFX10-NEXT: s_lshr_b32 s3, s5, s4
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3
; GFX10-NEXT: ; return to shader part epilog
%result = lshr <4 x i16> %value, %amount
%cast = bitcast <4 x i16> %result to <2 x i32>
ret <2 x i32> %cast
}
; FIXME
; define <5 x i16> @v_lshr_v5i16(<5 x i16> %value, <5 x i16> %amount) {
; %result = lshr <5 x i16> %value, %amount
; ret <5 x i16> %result
; }
; define amdgpu_ps <5 x i16> @s_lshr_v5i16(<5 x i16> inreg %value, <5 x i16> inreg %amount) {
; %result = lshr <5 x i16> %value, %amount
; ret <5 x i16> %result
; }
; define <3 x float> @v_lshr_v6i16(<6 x i16> %value, <6 x i16> %amount) {
; %result = lshr <6 x i16> %value, %amount
; %cast = bitcast <6 x i16> %result to <3 x float>
; ret <3 x float> %cast
; }
; define amdgpu_ps <3 x i32> @s_lshr_v6i16(<6 x i16> inreg %value, <6 x i16> inreg %amount) {
; %result = lshr <6 x i16> %value, %amount
; %cast = bitcast <6 x i16> %result to <3 x i32>
; ret <3 x i32> %cast
; }
define <4 x float> @v_lshr_v8i16(<8 x i16> %value, <8 x i16> %amount) {
; GFX6-LABEL: v_lshr_v8i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_and_b32_e32 v8, s4, v8
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, v8, v0
; GFX6-NEXT: v_and_b32_e32 v8, s4, v9
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v8, v1
; GFX6-NEXT: v_and_b32_e32 v8, s4, v10
; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v8, v2
; GFX6-NEXT: v_and_b32_e32 v8, s4, v11
; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v3, v8, v3
; GFX6-NEXT: v_and_b32_e32 v8, s4, v12
; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v4, v8, v4
; GFX6-NEXT: v_and_b32_e32 v8, s4, v13
; GFX6-NEXT: v_and_b32_e32 v5, s4, v5
; GFX6-NEXT: v_mov_b32_e32 v16, 0xffff
; GFX6-NEXT: v_lshrrev_b32_e32 v5, v8, v5
; GFX6-NEXT: v_and_b32_e32 v8, s4, v14
; GFX6-NEXT: v_and_b32_e32 v6, s4, v6
; GFX6-NEXT: v_lshrrev_b32_e32 v6, v8, v6
; GFX6-NEXT: v_and_b32_e32 v8, v15, v16
; GFX6-NEXT: v_and_b32_e32 v7, v7, v16
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v7, v8, v7
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; GFX6-NEXT: v_or_b32_e32 v2, v4, v2
; GFX6-NEXT: v_or_b32_e32 v3, v6, v3
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_lshr_v8i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b16_e32 v8, v4, v0
; GFX8-NEXT: v_lshrrev_b16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_lshrrev_b16_e32 v4, v5, v1
; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v1, v4, v1
; GFX8-NEXT: v_lshrrev_b16_e32 v4, v6, v2
; GFX8-NEXT: v_lshrrev_b16_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v2, v4, v2
; GFX8-NEXT: v_lshrrev_b16_e32 v4, v7, v3
; GFX8-NEXT: v_lshrrev_b16_sdwa v3, v7, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_or_b32_e32 v0, v8, v0
; GFX8-NEXT: v_or_b32_e32 v3, v4, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_lshr_v8i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_pk_lshrrev_b16 v0, v4, v0
; GFX9-NEXT: v_pk_lshrrev_b16 v1, v5, v1
; GFX9-NEXT: v_pk_lshrrev_b16 v2, v6, v2
; GFX9-NEXT: v_pk_lshrrev_b16 v3, v7, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_v8i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_pk_lshrrev_b16 v0, v4, v0
; GFX10-NEXT: v_pk_lshrrev_b16 v1, v5, v1
; GFX10-NEXT: v_pk_lshrrev_b16 v2, v6, v2
; GFX10-NEXT: v_pk_lshrrev_b16 v3, v7, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr <8 x i16> %value, %amount
%cast = bitcast <8 x i16> %result to <4 x float>
ret <4 x float> %cast
}
define amdgpu_ps <4 x i32> @s_lshr_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) {
; GFX6-LABEL: s_lshr_v8i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s16, 0xffff
; GFX6-NEXT: s_and_b32 s1, s1, s16
; GFX6-NEXT: s_and_b32 s0, s0, s16
; GFX6-NEXT: s_lshr_b32 s1, s1, s9
; GFX6-NEXT: s_and_b32 s3, s3, s16
; GFX6-NEXT: s_lshr_b32 s0, s0, s8
; GFX6-NEXT: s_and_b32 s2, s2, s16
; GFX6-NEXT: s_lshr_b32 s3, s3, s11
; GFX6-NEXT: s_and_b32 s5, s5, s16
; GFX6-NEXT: s_and_b32 s7, s7, s16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_lshr_b32 s2, s2, s10
; GFX6-NEXT: s_and_b32 s4, s4, s16
; GFX6-NEXT: s_lshr_b32 s5, s5, s13
; GFX6-NEXT: s_and_b32 s6, s6, s16
; GFX6-NEXT: s_lshr_b32 s7, s7, s15
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s3, 16
; GFX6-NEXT: s_lshr_b32 s4, s4, s12
; GFX6-NEXT: s_lshr_b32 s6, s6, s14
; GFX6-NEXT: s_or_b32 s1, s2, s1
; GFX6-NEXT: s_lshl_b32 s2, s5, 16
; GFX6-NEXT: s_lshl_b32 s3, s7, 16
; GFX6-NEXT: s_or_b32 s2, s4, s2
; GFX6-NEXT: s_or_b32 s3, s6, s3
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_lshr_v8i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_mov_b32 s12, 0xffff
; GFX8-NEXT: s_lshr_b32 s8, s0, 16
; GFX8-NEXT: s_and_b32 s0, s0, s12
; GFX8-NEXT: s_lshr_b32 s13, s4, 16
; GFX8-NEXT: s_lshr_b32 s9, s1, 16
; GFX8-NEXT: s_and_b32 s1, s1, s12
; GFX8-NEXT: s_lshr_b32 s14, s5, 16
; GFX8-NEXT: s_lshr_b32 s0, s0, s4
; GFX8-NEXT: s_lshr_b32 s4, s8, s13
; GFX8-NEXT: s_lshr_b32 s10, s2, 16
; GFX8-NEXT: s_and_b32 s2, s2, s12
; GFX8-NEXT: s_lshr_b32 s15, s6, 16
; GFX8-NEXT: s_lshr_b32 s1, s1, s5
; GFX8-NEXT: s_lshr_b32 s5, s9, s14
; GFX8-NEXT: s_lshl_b32 s4, s4, 16
; GFX8-NEXT: s_and_b32 s0, s0, s12
; GFX8-NEXT: s_lshr_b32 s11, s3, 16
; GFX8-NEXT: s_and_b32 s3, s3, s12
; GFX8-NEXT: s_lshr_b32 s16, s7, 16
; GFX8-NEXT: s_lshr_b32 s2, s2, s6
; GFX8-NEXT: s_lshr_b32 s6, s10, s15
; GFX8-NEXT: s_or_b32 s0, s4, s0
; GFX8-NEXT: s_lshl_b32 s4, s5, 16
; GFX8-NEXT: s_and_b32 s1, s1, s12
; GFX8-NEXT: s_lshr_b32 s3, s3, s7
; GFX8-NEXT: s_lshr_b32 s7, s11, s16
; GFX8-NEXT: s_or_b32 s1, s4, s1
; GFX8-NEXT: s_lshl_b32 s4, s6, 16
; GFX8-NEXT: s_and_b32 s2, s2, s12
; GFX8-NEXT: s_or_b32 s2, s4, s2
; GFX8-NEXT: s_lshl_b32 s4, s7, 16
; GFX8-NEXT: s_and_b32 s3, s3, s12
; GFX8-NEXT: s_or_b32 s3, s4, s3
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_lshr_v8i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b32 s9, 0xffff
; GFX9-NEXT: s_lshr_b32 s8, s0, 16
; GFX9-NEXT: s_and_b32 s0, s0, s9
; GFX9-NEXT: s_lshr_b32 s10, s4, 16
; GFX9-NEXT: s_lshr_b32 s0, s0, s4
; GFX9-NEXT: s_lshr_b32 s4, s8, s10
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4
; GFX9-NEXT: s_lshr_b32 s4, s1, 16
; GFX9-NEXT: s_and_b32 s1, s1, s9
; GFX9-NEXT: s_lshr_b32 s8, s5, 16
; GFX9-NEXT: s_lshr_b32 s1, s1, s5
; GFX9-NEXT: s_lshr_b32 s4, s4, s8
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4
; GFX9-NEXT: s_lshr_b32 s4, s2, 16
; GFX9-NEXT: s_and_b32 s2, s2, s9
; GFX9-NEXT: s_lshr_b32 s5, s6, 16
; GFX9-NEXT: s_lshr_b32 s2, s2, s6
; GFX9-NEXT: s_lshr_b32 s4, s4, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4
; GFX9-NEXT: s_lshr_b32 s4, s3, 16
; GFX9-NEXT: s_and_b32 s3, s3, s9
; GFX9-NEXT: s_lshr_b32 s5, s7, 16
; GFX9-NEXT: s_lshr_b32 s3, s3, s7
; GFX9-NEXT: s_lshr_b32 s4, s4, s5
; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_v8i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_mov_b32 s8, 0xffff
; GFX10-NEXT: s_lshr_b32 s9, s0, 16
; GFX10-NEXT: s_and_b32 s0, s0, s8
; GFX10-NEXT: s_lshr_b32 s10, s4, 16
; GFX10-NEXT: s_lshr_b32 s0, s0, s4
; GFX10-NEXT: s_lshr_b32 s4, s9, s10
; GFX10-NEXT: s_lshr_b32 s9, s1, 16
; GFX10-NEXT: s_and_b32 s1, s1, s8
; GFX10-NEXT: s_lshr_b32 s10, s5, 16
; GFX10-NEXT: s_lshr_b32 s1, s1, s5
; GFX10-NEXT: s_lshr_b32 s5, s9, s10
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4
; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5
; GFX10-NEXT: s_lshr_b32 s4, s2, 16
; GFX10-NEXT: s_and_b32 s2, s2, s8
; GFX10-NEXT: s_lshr_b32 s5, s6, 16
; GFX10-NEXT: s_lshr_b32 s2, s2, s6
; GFX10-NEXT: s_lshr_b32 s4, s4, s5
; GFX10-NEXT: s_lshr_b32 s5, s3, 16
; GFX10-NEXT: s_and_b32 s3, s3, s8
; GFX10-NEXT: s_lshr_b32 s6, s7, 16
; GFX10-NEXT: s_lshr_b32 s3, s3, s7
; GFX10-NEXT: s_lshr_b32 s5, s5, s6
; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4
; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s5
; GFX10-NEXT: ; return to shader part epilog
%result = lshr <8 x i16> %value, %amount
%cast = bitcast <8 x i16> %result to <4 x i32>
ret <4 x i32> %cast
}
define i64 @v_lshr_i64(i64 %value, i64 %amount) {
; GFX6-LABEL: v_lshr_i64:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_lshr_i64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_lshr_i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr i64 %value, %amount
ret i64 %result
}
define i64 @v_lshr_i64_63(i64 %value) {
; GCN-LABEL: v_lshr_i64_63:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v0, 31, v1
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i64_63:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 31, v1
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr i64 %value, 63
ret i64 %result
}
define i64 @v_lshr_i64_33(i64 %value) {
; GCN-LABEL: v_lshr_i64_33:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_lshrrev_b32_e32 v0, 1, v1
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i64_33:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 1, v1
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr i64 %value, 33
ret i64 %result
}
define i64 @v_lshr_i64_32(i64 %value) {
; GCN-LABEL: v_lshr_i64_32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i64_32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v0, v1
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr i64 %value, 32
ret i64 %result
}
define i64 @v_lshr_i64_31(i64 %value) {
; GFX6-LABEL: v_lshr_i64_31:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 31
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_lshr_i64_31:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_lshr_i64_31:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i64_31:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1]
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr i64 %value, 31
ret i64 %result
}
define amdgpu_ps i64 @s_lshr_i64(i64 inreg %value, i64 inreg %amount) {
; GCN-LABEL: s_lshr_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_i64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i64 %value, %amount
ret i64 %result
}
define amdgpu_ps i64 @s_lshr_i64_63(i64 inreg %value) {
; GCN-LABEL: s_lshr_i64_63:
; GCN: ; %bb.0:
; GCN-NEXT: s_lshr_b32 s0, s1, 31
; GCN-NEXT: s_mov_b32 s1, 0
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_i64_63:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s0, s1, 31
; GFX10-NEXT: s_mov_b32 s1, 0
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i64 %value, 63
ret i64 %result
}
define amdgpu_ps i64 @s_lshr_i64_33(i64 inreg %value) {
; GCN-LABEL: s_lshr_i64_33:
; GCN: ; %bb.0:
; GCN-NEXT: s_lshr_b32 s0, s1, 1
; GCN-NEXT: s_mov_b32 s1, 0
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_i64_33:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s0, s1, 1
; GFX10-NEXT: s_mov_b32 s1, 0
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i64 %value, 33
ret i64 %result
}
define amdgpu_ps i64 @s_lshr_i64_32(i64 inreg %value) {
; GCN-LABEL: s_lshr_i64_32:
; GCN: ; %bb.0:
; GCN-NEXT: s_mov_b32 s0, s1
; GCN-NEXT: s_mov_b32 s1, 0
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_i64_32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_mov_b32 s0, s1
; GFX10-NEXT: s_mov_b32 s1, 0
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i64 %value, 32
ret i64 %result
}
define amdgpu_ps i64 @s_lshr_i64_31(i64 inreg %value) {
; GCN-LABEL: s_lshr_i64_31:
; GCN: ; %bb.0:
; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], 31
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_i64_31:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], 31
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i64 %value, 31
ret i64 %result
}
define amdgpu_ps <2 x float> @lshr_i64_sv(i64 inreg %value, i64 %amount) {
; GFX6-LABEL: lshr_i64_sv:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshr_b64 v[0:1], s[0:1], v0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: lshr_i64_sv:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1]
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: lshr_i64_sv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1]
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: lshr_i64_sv:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshrrev_b64 v[0:1], v0, s[0:1]
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i64 %value, %amount
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
}
define amdgpu_ps <2 x float> @lshr_i64_vs(i64 %value, i64 inreg %amount) {
; GFX6-LABEL: lshr_i64_vs:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], s0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: lshr_i64_vs:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1]
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: lshr_i64_vs:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1]
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: lshr_i64_vs:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshrrev_b64 v[0:1], s0, v[0:1]
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i64 %value, %amount
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
}
define <2 x i64> @v_lshr_v2i64(<2 x i64> %value, <2 x i64> %amount) {
; GFX6-LABEL: v_lshr_v2i64:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], v4
; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], v6
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_lshr_v2i64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1]
; GFX8-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_lshr_v2i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1]
; GFX9-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_v2i64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b64 v[0:1], v4, v[0:1]
; GFX10-NEXT: v_lshrrev_b64 v[2:3], v6, v[2:3]
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr <2 x i64> %value, %amount
ret <2 x i64> %result
}
define <2 x i64> @v_lshr_v2i64_31(<2 x i64> %value) {
; GFX6-LABEL: v_lshr_v2i64_31:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshr_b64 v[0:1], v[0:1], 31
; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], 31
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_lshr_v2i64_31:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1]
; GFX8-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3]
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_lshr_v2i64_31:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1]
; GFX9-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_v2i64_31:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b64 v[0:1], 31, v[0:1]
; GFX10-NEXT: v_lshrrev_b64 v[2:3], 31, v[2:3]
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr <2 x i64> %value, <i64 31, i64 31>
ret <2 x i64> %result
}
define amdgpu_ps <2 x i64> @s_lshr_v2i64(<2 x i64> inreg %value, <2 x i64> inreg %amount) {
; GCN-LABEL: s_lshr_v2i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], s4
; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], s6
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_v2i64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s4
; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s6
; GFX10-NEXT: ; return to shader part epilog
%result = lshr <2 x i64> %value, %amount
ret <2 x i64> %result
}
define i65 @v_lshr_i65(i65 %value, i65 %amount) {
; GFX6-LABEL: v_lshr_i65:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_and_b32_e32 v4, 1, v2
; GFX6-NEXT: v_mov_b32_e32 v5, 0
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 64, v3
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 64, v3
; GFX6-NEXT: v_lshr_b64 v[6:7], v[0:1], v3
; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], v8
; GFX6-NEXT: v_lshr_b64 v[10:11], v[4:5], v3
; GFX6-NEXT: v_lshr_b64 v[4:5], v[4:5], v2
; GFX6-NEXT: v_or_b32_e32 v6, v6, v8
; GFX6-NEXT: v_or_b32_e32 v7, v7, v9
; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3
; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc
; GFX6-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
; GFX6-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_lshr_i65:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_and_b32_e32 v4, 1, v2
; GFX8-NEXT: v_mov_b32_e32 v5, 0
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 64, v3
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 64, v3
; GFX8-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1]
; GFX8-NEXT: v_lshlrev_b64 v[8:9], v8, v[4:5]
; GFX8-NEXT: v_lshrrev_b64 v[10:11], v3, v[4:5]
; GFX8-NEXT: v_lshrrev_b64 v[4:5], v2, v[4:5]
; GFX8-NEXT: v_or_b32_e32 v6, v6, v8
; GFX8-NEXT: v_or_b32_e32 v7, v7, v9
; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3
; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
; GFX8-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_lshr_i65:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v4, 1, v2
; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_sub_u32_e32 v8, 64, v3
; GFX9-NEXT: v_subrev_u32_e32 v2, 64, v3
; GFX9-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1]
; GFX9-NEXT: v_lshlrev_b64 v[8:9], v8, v[4:5]
; GFX9-NEXT: v_lshrrev_b64 v[10:11], v3, v[4:5]
; GFX9-NEXT: v_lshrrev_b64 v[4:5], v2, v[4:5]
; GFX9-NEXT: v_or_b32_e32 v6, v6, v8
; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3
; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v7, vcc
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v3
; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v10, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i65:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v5, 0
; GFX10-NEXT: v_and_b32_e32 v4, 1, v2
; GFX10-NEXT: v_sub_nc_u32_e32 v2, 64, v3
; GFX10-NEXT: v_subrev_nc_u32_e32 v10, 64, v3
; GFX10-NEXT: v_lshrrev_b64 v[6:7], v3, v[0:1]
; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v3
; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 0, v3
; GFX10-NEXT: v_lshlrev_b64 v[8:9], v2, v[4:5]
; GFX10-NEXT: v_lshrrev_b64 v[10:11], v10, v[4:5]
; GFX10-NEXT: v_lshrrev_b64 v[4:5], v3, v[4:5]
; GFX10-NEXT: v_or_b32_e32 v2, v6, v8
; GFX10-NEXT: v_or_b32_e32 v6, v7, v9
; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v5, v11, v6, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, v0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v1, s4
; GFX10-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr i65 %value, %amount
ret i65 %result
}
define i65 @v_lshr_i65_33(i65 %value) {
; GFX6-LABEL: v_lshr_i65_33:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v3, v1
; GFX6-NEXT: v_and_b32_e32 v0, 1, v2
; GFX6-NEXT: v_mov_b32_e32 v1, 0
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 31
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v3
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
; GFX6-NEXT: v_mov_b32_e32 v2, 0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_lshr_i65_33:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v3, v1
; GFX8-NEXT: v_and_b32_e32 v0, 1, v2
; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v3
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-NEXT: v_mov_b32_e32 v2, 0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_lshr_i65_33:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v3, v1
; GFX9-NEXT: v_and_b32_e32 v0, 1, v2
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v3
; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_lshr_i65_33:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v3, v1
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_and_b32_e32 v0, 1, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 1, v3
; GFX10-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]
; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = lshr i65 %value, 33
ret i65 %result
}
define amdgpu_ps i65 @s_lshr_i65(i65 inreg %value, i65 inreg %amount) {
; GCN-LABEL: s_lshr_i65:
; GCN: ; %bb.0:
; GCN-NEXT: s_and_b64 s[4:5], s[2:3], 1
; GCN-NEXT: s_sub_i32 s10, s3, 64
; GCN-NEXT: s_sub_i32 s8, 64, s3
; GCN-NEXT: s_cmp_lt_u32 s3, 64
; GCN-NEXT: s_cselect_b32 s11, 1, 0
; GCN-NEXT: s_cmp_eq_u32 s3, 0
; GCN-NEXT: s_cselect_b32 s12, 1, 0
; GCN-NEXT: s_lshr_b64 s[6:7], s[4:5], s3
; GCN-NEXT: s_lshr_b64 s[2:3], s[0:1], s3
; GCN-NEXT: s_lshl_b64 s[8:9], s[4:5], s8
; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
; GCN-NEXT: s_lshr_b64 s[4:5], s[4:5], s10
; GCN-NEXT: s_cmp_lg_u32 s11, 0
; GCN-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5]
; GCN-NEXT: s_cmp_lg_u32 s12, 0
; GCN-NEXT: s_cselect_b64 s[0:1], s[0:1], s[2:3]
; GCN-NEXT: s_cmp_lg_u32 s11, 0
; GCN-NEXT: s_cselect_b64 s[2:3], s[6:7], 0
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_i65:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b64 s[4:5], s[2:3], 1
; GFX10-NEXT: s_sub_i32 s10, s3, 64
; GFX10-NEXT: s_sub_i32 s2, 64, s3
; GFX10-NEXT: s_cmp_lt_u32 s3, 64
; GFX10-NEXT: s_cselect_b32 s11, 1, 0
; GFX10-NEXT: s_cmp_eq_u32 s3, 0
; GFX10-NEXT: s_cselect_b32 s12, 1, 0
; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s3
; GFX10-NEXT: s_lshl_b64 s[8:9], s[4:5], s2
; GFX10-NEXT: s_lshr_b64 s[2:3], s[4:5], s3
; GFX10-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], s10
; GFX10-NEXT: s_cmp_lg_u32 s11, 0
; GFX10-NEXT: s_cselect_b64 s[4:5], s[6:7], s[4:5]
; GFX10-NEXT: s_cmp_lg_u32 s12, 0
; GFX10-NEXT: s_cselect_b64 s[0:1], s[0:1], s[4:5]
; GFX10-NEXT: s_cmp_lg_u32 s11, 0
; GFX10-NEXT: s_cselect_b64 s[2:3], s[2:3], 0
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i65 %value, %amount
ret i65 %result
}
define amdgpu_ps i65 @s_lshr_i65_33(i65 inreg %value) {
; GCN-LABEL: s_lshr_i65_33:
; GCN: ; %bb.0:
; GCN-NEXT: s_and_b64 s[2:3], s[2:3], 1
; GCN-NEXT: s_lshr_b32 s0, s1, 1
; GCN-NEXT: s_mov_b32 s1, 0
; GCN-NEXT: s_lshl_b64 s[4:5], s[2:3], 31
; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GCN-NEXT: s_lshr_b32 s2, s3, 1
; GCN-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_lshr_i65_33:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_and_b64 s[2:3], s[2:3], 1
; GFX10-NEXT: s_lshr_b32 s0, s1, 1
; GFX10-NEXT: s_mov_b32 s1, 0
; GFX10-NEXT: s_lshl_b64 s[4:5], s[2:3], 31
; GFX10-NEXT: s_lshr_b32 s2, s3, 1
; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX10-NEXT: ; return to shader part epilog
%result = lshr i65 %value, 33
ret i65 %result
}
; FIXME: Argument lowering asserts
; define <2 x i65> @v_lshr_v2i65(<2 x i65> %value, <2 x i65> %amount) {
; %result = lshr <2 x i65> %value, %amount
; ret <2 x i65> %result
; }
; define amdgpu_ps <2 x i65> @s_lshr_v2i65(<2 x i65> inreg %value, <2 x i65> inreg %amount) {
; %result = lshr <2 x i65> %value, %amount
; ret <2 x i65> %result
; }
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