eb88e793ff
Try to stress constant bus restriction enforcement since some of these are broken for GlobalISel. Split the r600 test because some of these cases don't compile (and all the ones using return values are discarded).
238 lines
7.7 KiB
LLVM
238 lines
7.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope -check-prefixes=R600 %s
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; BFI_INT Definition pattern from ISA docs
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; (y & x) | (z & ~x)
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;
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define amdgpu_kernel void @bfi_def(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
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; R600-LABEL: bfi_def:
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; R600: ; %bb.0: ; %entry
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; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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; R600-NEXT: BFI_INT * T1.X, KC0[2].Z, KC0[2].W, KC0[3].X,
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entry:
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%0 = xor i32 %x, -1
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%1 = and i32 %z, %0
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%2 = and i32 %y, %x
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%3 = or i32 %1, %2
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; SHA-256 Ch function
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; z ^ (x & (y ^ z))
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define amdgpu_kernel void @bfi_sha256_ch(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
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; R600-LABEL: bfi_sha256_ch:
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; R600: ; %bb.0: ; %entry
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; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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; R600-NEXT: BFI_INT * T1.X, KC0[2].Z, KC0[2].W, KC0[3].X,
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entry:
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%0 = xor i32 %y, %z
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%1 = and i32 %x, %0
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%2 = xor i32 %z, %1
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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; SHA-256 Ma function
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; ((x & z) | (y & (x | z)))
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define amdgpu_kernel void @bfi_sha256_ma(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
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; R600-LABEL: bfi_sha256_ma:
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; R600: ; %bb.0: ; %entry
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; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: XOR_INT * T0.W, KC0[2].Z, KC0[2].W,
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; R600-NEXT: BFI_INT * T0.X, PV.W, KC0[3].X, KC0[2].W,
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; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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entry:
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%0 = and i32 %x, %z
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%1 = or i32 %x, %z
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%2 = and i32 %y, %1
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%3 = or i32 %0, %2
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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define <2 x i32> @v_bitselect_v2i32_pat1(<2 x i32> %a, <2 x i32> %b, <2 x i32> %mask) {
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; R600-LABEL: v_bitselect_v2i32_pat1:
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; R600: ; %bb.0:
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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%xor.0 = xor <2 x i32> %a, %mask
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%and = and <2 x i32> %xor.0, %b
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%bitselect = xor <2 x i32> %and, %mask
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ret <2 x i32> %bitselect
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}
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define i64 @v_bitselect_i64_pat_0(i64 %a, i64 %b, i64 %mask) {
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; R600-LABEL: v_bitselect_i64_pat_0:
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; R600: ; %bb.0:
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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%and0 = and i64 %a, %b
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%not.a = xor i64 %a, -1
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%and1 = and i64 %not.a, %mask
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%bitselect = or i64 %and0, %and1
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ret i64 %bitselect
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}
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define i64 @v_bitselect_i64_pat_1(i64 %a, i64 %b, i64 %mask) {
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; R600-LABEL: v_bitselect_i64_pat_1:
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; R600: ; %bb.0:
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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%xor.0 = xor i64 %a, %mask
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%and = and i64 %xor.0, %b
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%bitselect = xor i64 %and, %mask
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ret i64 %bitselect
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}
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define i64 @v_bitselect_i64_pat_2(i64 %a, i64 %b, i64 %mask) {
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; R600-LABEL: v_bitselect_i64_pat_2:
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; R600: ; %bb.0:
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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%xor.0 = xor i64 %a, %mask
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%and = and i64 %xor.0, %b
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%bitselect = xor i64 %and, %mask
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ret i64 %bitselect
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}
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define i64 @v_bfi_sha256_ma_i64(i64 %x, i64 %y, i64 %z) {
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; R600-LABEL: v_bfi_sha256_ma_i64:
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; R600: ; %bb.0: ; %entry
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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entry:
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%and0 = and i64 %x, %z
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%or0 = or i64 %x, %z
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%and1 = and i64 %y, %or0
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%or1 = or i64 %and0, %and1
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ret i64 %or1
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}
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define amdgpu_kernel void @s_bitselect_i64_pat_0(i64 %a, i64 %b, i64 %mask) {
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; R600-LABEL: s_bitselect_i64_pat_0:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: MOV * T0.W, KC0[3].Y,
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; R600-NEXT: BFI_INT * T0.W, KC0[2].Y, KC0[2].W, PV.W,
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; R600-NEXT: MOV * T1.W, KC0[3].Z,
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; R600-NEXT: BFI_INT T1.W, KC0[2].Z, KC0[3].X, PV.W,
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; R600-NEXT: ADDC_UINT * T2.W, T0.W, literal.x,
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; R600-NEXT: 10(1.401298e-44), 0(0.000000e+00)
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; R600-NEXT: ADD_INT * T0.Y, PV.W, PS,
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; R600-NEXT: ADD_INT T0.X, T0.W, literal.x,
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; R600-NEXT: MOV * T1.X, literal.y,
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; R600-NEXT: 10(1.401298e-44), 0(0.000000e+00)
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%and0 = and i64 %a, %b
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%not.a = xor i64 %a, -1
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%and1 = and i64 %not.a, %mask
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%bitselect = or i64 %and0, %and1
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%scalar.use = add i64 %bitselect, 10
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store i64 %scalar.use, i64 addrspace(1)* undef
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ret void
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}
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define amdgpu_kernel void @s_bitselect_i64_pat_1(i64 %a, i64 %b, i64 %mask) {
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; R600-LABEL: s_bitselect_i64_pat_1:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: MOV * T0.W, KC0[3].Y,
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; R600-NEXT: BFI_INT * T0.W, KC0[2].W, KC0[2].Y, PV.W,
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; R600-NEXT: MOV * T1.W, KC0[3].Z,
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; R600-NEXT: BFI_INT T1.W, KC0[3].X, KC0[2].Z, PV.W,
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; R600-NEXT: ADDC_UINT * T2.W, T0.W, literal.x,
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; R600-NEXT: 10(1.401298e-44), 0(0.000000e+00)
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; R600-NEXT: ADD_INT * T0.Y, PV.W, PS,
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; R600-NEXT: ADD_INT T0.X, T0.W, literal.x,
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; R600-NEXT: MOV * T1.X, literal.y,
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; R600-NEXT: 10(1.401298e-44), 0(0.000000e+00)
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%xor.0 = xor i64 %a, %mask
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%and = and i64 %xor.0, %b
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%bitselect = xor i64 %and, %mask
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%scalar.use = add i64 %bitselect, 10
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store i64 %scalar.use, i64 addrspace(1)* undef
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ret void
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}
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define amdgpu_kernel void @s_bitselect_i64_pat_2(i64 %a, i64 %b, i64 %mask) {
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; R600-LABEL: s_bitselect_i64_pat_2:
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; R600: ; %bb.0:
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; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: MOV * T0.W, KC0[3].Y,
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; R600-NEXT: BFI_INT * T0.W, KC0[2].W, KC0[2].Y, PV.W,
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; R600-NEXT: MOV * T1.W, KC0[3].Z,
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; R600-NEXT: BFI_INT T1.W, KC0[3].X, KC0[2].Z, PV.W,
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; R600-NEXT: ADDC_UINT * T2.W, T0.W, literal.x,
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; R600-NEXT: 10(1.401298e-44), 0(0.000000e+00)
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; R600-NEXT: ADD_INT * T0.Y, PV.W, PS,
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; R600-NEXT: ADD_INT T0.X, T0.W, literal.x,
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; R600-NEXT: MOV * T1.X, literal.y,
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; R600-NEXT: 10(1.401298e-44), 0(0.000000e+00)
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%xor.0 = xor i64 %a, %mask
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%and = and i64 %xor.0, %b
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%bitselect = xor i64 %and, %mask
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%scalar.use = add i64 %bitselect, 10
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store i64 %scalar.use, i64 addrspace(1)* undef
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ret void
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}
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define amdgpu_kernel void @s_bfi_sha256_ma_i64(i64 %x, i64 %y, i64 %z) {
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; R600-LABEL: s_bfi_sha256_ma_i64:
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; R600: ; %bb.0: ; %entry
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; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: ALU clause starting at 4:
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; R600-NEXT: XOR_INT * T0.W, KC0[2].Y, KC0[2].W,
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; R600-NEXT: BFI_INT T0.W, PV.W, KC0[3].Y, KC0[2].W,
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; R600-NEXT: XOR_INT * T1.W, KC0[2].Z, KC0[3].X,
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; R600-NEXT: BFI_INT T1.W, PS, KC0[3].Z, KC0[3].X,
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; R600-NEXT: ADDC_UINT * T2.W, PV.W, literal.x,
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; R600-NEXT: 10(1.401298e-44), 0(0.000000e+00)
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; R600-NEXT: ADD_INT * T0.Y, PV.W, PS,
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; R600-NEXT: ADD_INT T0.X, T0.W, literal.x,
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; R600-NEXT: MOV * T1.X, literal.y,
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; R600-NEXT: 10(1.401298e-44), 0(0.000000e+00)
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entry:
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%and0 = and i64 %x, %z
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%or0 = or i64 %x, %z
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%and1 = and i64 %y, %or0
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%or1 = or i64 %and0, %and1
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%scalar.use = add i64 %or1, 10
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store i64 %scalar.use, i64 addrspace(1)* undef
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ret void
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}
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