18f9351223
The compiler was generating symbols in the final code object for local branch target labels. This bloats the code object, slows down the loader, and is only used to simplify disassembly. Use '--symbolize-operands' with llvm-objdump to improve readability of the branch target operands in disassembly. Fixes: SWDEV-312223 Reviewed By: scott.linder Differential Revision: https://reviews.llvm.org/D114273
302 lines
6.5 KiB
LLVM
302 lines
6.5 KiB
LLVM
; RUN: opt -S -mtriple=amdgcn-- -codegenprepare < %s | FileCheck -check-prefix=OPT %s
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; RUN: opt -S -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -codegenprepare < %s | FileCheck -check-prefix=OPT %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; This particular case will actually be worse in terms of code size
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; from sinking into both.
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; OPT-LABEL: @sink_ubfe_i32(
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; OPT: entry:
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; OPT-NEXT: br i1
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; OPT: bb0:
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; OPT: %0 = lshr i32 %arg1, 8
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; OPT-NEXT: %val0 = and i32 %0, 255
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; OPT: br label
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; OPT: bb1:
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; OPT: %1 = lshr i32 %arg1, 8
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; OPT-NEXT: %val1 = and i32 %1, 127
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; OPT: br label
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; OPT: ret:
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; OPT: store
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; OPT: ret
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; GCN-LABEL: {{^}}sink_ubfe_i32:
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; GCN-NOT: lshr
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; GCN: s_cbranch_scc{{[0-1]}}
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; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70008
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; GCN: .LBB0_3:
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; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80008
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; GCN: buffer_store_dword
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; GCN: s_endpgm
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define amdgpu_kernel void @sink_ubfe_i32(i32 addrspace(1)* %out, i32 %arg1) #0 {
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entry:
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%shr = lshr i32 %arg1, 8
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br i1 undef, label %bb0, label %bb1
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bb0:
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%val0 = and i32 %shr, 255
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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bb1:
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%val1 = and i32 %shr, 127
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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ret:
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%phi = phi i32 [ %val0, %bb0 ], [ %val1, %bb1 ]
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store i32 %phi, i32 addrspace(1)* %out
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ret void
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}
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; OPT-LABEL: @sink_sbfe_i32(
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; OPT: entry:
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; OPT-NEXT: br i1
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; OPT: bb0:
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; OPT: %0 = ashr i32 %arg1, 8
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; OPT-NEXT: %val0 = and i32 %0, 255
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; OPT: br label
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; OPT: bb1:
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; OPT: %1 = ashr i32 %arg1, 8
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; OPT-NEXT: %val1 = and i32 %1, 127
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; OPT: br label
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; OPT: ret:
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; OPT: store
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; OPT: ret
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; GCN-LABEL: {{^}}sink_sbfe_i32:
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define amdgpu_kernel void @sink_sbfe_i32(i32 addrspace(1)* %out, i32 %arg1) #0 {
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entry:
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%shr = ashr i32 %arg1, 8
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br i1 undef, label %bb0, label %bb1
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bb0:
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%val0 = and i32 %shr, 255
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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bb1:
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%val1 = and i32 %shr, 127
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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ret:
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%phi = phi i32 [ %val0, %bb0 ], [ %val1, %bb1 ]
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store i32 %phi, i32 addrspace(1)* %out
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ret void
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}
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; OPT-LABEL: @sink_ubfe_i16(
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; OPT: entry:
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; OPT-NEXT: br i1
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; OPT: bb0:
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; OPT: %0 = lshr i16 %arg1, 4
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; OPT-NEXT: %val0 = and i16 %0, 255
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; OPT: br label
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; OPT: bb1:
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; OPT: %1 = lshr i16 %arg1, 4
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; OPT-NEXT: %val1 = and i16 %1, 127
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; OPT: br label
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; OPT: ret:
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; OPT: store
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; OPT: ret
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; For GFX8: since i16 is legal type, we cannot sink lshr into .LBBs.
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; GCN-LABEL: {{^}}sink_ubfe_i16:
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; GCN-NOT: lshr
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; VI: s_load_dword [[ARG:s[0-9]+]], s[0:1], 0x2c
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; VI: s_bfe_u32 [[BFE:s[0-9]+]], [[ARG]], 0xc0004
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; GCN: s_cbranch_scc{{[0-1]}}
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; SI: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70004
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; VI: v_mov_b32_e32 v{{[0-9]+}}, 0x7f
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; GCN: .LBB2_3:
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; SI: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80004
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; VI: v_mov_b32_e32 v{{[0-9]+}}, 0xff
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; GCN: buffer_store_short
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; GCN: s_endpgm
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define amdgpu_kernel void @sink_ubfe_i16(i16 addrspace(1)* %out, i16 %arg1) #0 {
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entry:
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%shr = lshr i16 %arg1, 4
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br i1 undef, label %bb0, label %bb1
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bb0:
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%val0 = and i16 %shr, 255
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store volatile i16 0, i16 addrspace(1)* undef
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br label %ret
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bb1:
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%val1 = and i16 %shr, 127
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store volatile i16 0, i16 addrspace(1)* undef
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br label %ret
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ret:
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%phi = phi i16 [ %val0, %bb0 ], [ %val1, %bb1 ]
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store i16 %phi, i16 addrspace(1)* %out
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ret void
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}
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; We don't really want to sink this one since it isn't reducible to a
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; 32-bit BFE on one half of the integer.
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; OPT-LABEL: @sink_ubfe_i64_span_midpoint(
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; OPT: entry:
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; OPT-NOT: lshr
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; OPT: br i1
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; OPT: bb0:
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; OPT: %0 = lshr i64 %arg1, 30
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; OPT-NEXT: %val0 = and i64 %0, 255
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; OPT: bb1:
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; OPT: %1 = lshr i64 %arg1, 30
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; OPT-NEXT: %val1 = and i64 %1, 127
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; OPT: ret:
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; OPT: store
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; OPT: ret
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; GCN-LABEL: {{^}}sink_ubfe_i64_span_midpoint:
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; GCN: s_cbranch_scc{{[0-1]}} .LBB3_2
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; GCN: v_alignbit_b32 v[[LO:[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, 30
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; GCN: v_and_b32_e32 v{{[0-9]+}}, 0x7f, v[[LO]]
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; GCN: .LBB3_3:
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; GCN: v_and_b32_e32 v{{[0-9]+}}, 0xff, v[[LO]]
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; GCN: buffer_store_dwordx2
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define amdgpu_kernel void @sink_ubfe_i64_span_midpoint(i64 addrspace(1)* %out, i64 %arg1) #0 {
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entry:
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%shr = lshr i64 %arg1, 30
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br i1 undef, label %bb0, label %bb1
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bb0:
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%val0 = and i64 %shr, 255
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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bb1:
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%val1 = and i64 %shr, 127
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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ret:
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%phi = phi i64 [ %val0, %bb0 ], [ %val1, %bb1 ]
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store i64 %phi, i64 addrspace(1)* %out
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ret void
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}
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; OPT-LABEL: @sink_ubfe_i64_low32(
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; OPT: entry:
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; OPT-NOT: lshr
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; OPT: br i1
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; OPT: bb0:
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; OPT: %0 = lshr i64 %arg1, 15
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; OPT-NEXT: %val0 = and i64 %0, 255
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; OPT: bb1:
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; OPT: %1 = lshr i64 %arg1, 15
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; OPT-NEXT: %val1 = and i64 %1, 127
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; OPT: ret:
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; OPT: store
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; OPT: ret
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; GCN-LABEL: {{^}}sink_ubfe_i64_low32:
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; GCN: s_cbranch_scc{{[0-1]}} .LBB4_2
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; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7000f
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; GCN: .LBB4_3:
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; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x8000f
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; GCN: buffer_store_dwordx2
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define amdgpu_kernel void @sink_ubfe_i64_low32(i64 addrspace(1)* %out, i64 %arg1) #0 {
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entry:
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%shr = lshr i64 %arg1, 15
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br i1 undef, label %bb0, label %bb1
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bb0:
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%val0 = and i64 %shr, 255
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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bb1:
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%val1 = and i64 %shr, 127
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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ret:
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%phi = phi i64 [ %val0, %bb0 ], [ %val1, %bb1 ]
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store i64 %phi, i64 addrspace(1)* %out
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ret void
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}
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; OPT-LABEL: @sink_ubfe_i64_high32(
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; OPT: entry:
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; OPT-NOT: lshr
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; OPT: br i1
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; OPT: bb0:
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; OPT: %0 = lshr i64 %arg1, 35
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; OPT-NEXT: %val0 = and i64 %0, 255
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; OPT: bb1:
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; OPT: %1 = lshr i64 %arg1, 35
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; OPT-NEXT: %val1 = and i64 %1, 127
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; OPT: ret:
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; OPT: store
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; OPT: ret
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; GCN-LABEL: {{^}}sink_ubfe_i64_high32:
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; GCN: s_cbranch_scc{{[0-1]}} .LBB5_2
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; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70003
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; GCN: .LBB5_3:
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; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80003
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; GCN: buffer_store_dwordx2
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define amdgpu_kernel void @sink_ubfe_i64_high32(i64 addrspace(1)* %out, i64 %arg1) #0 {
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entry:
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%shr = lshr i64 %arg1, 35
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br i1 undef, label %bb0, label %bb1
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bb0:
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%val0 = and i64 %shr, 255
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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bb1:
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%val1 = and i64 %shr, 127
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store volatile i32 0, i32 addrspace(1)* undef
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br label %ret
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ret:
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%phi = phi i64 [ %val0, %bb0 ], [ %val1, %bb1 ]
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store i64 %phi, i64 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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