19727e31fb
ctlz/cttz get lowered to the set of target opcodes This change enables the ISel to select SALU or VALU form according to the SDNode divergence. CTLZ - S_FLBIT_I32_B32 if uniform and V_FFBH_U32_e64 if divergent CTTZ - S_FF1_I32_B32 if uniform and V_FFBL_B32_e64 if divergent Also @llvm.amdgcn.sffbh.i32 gets lowered to S_FLBIT_I32 if uniform and V_FFBH_I32_e64 if divergent NOTE: 64bit versions S_FF1_I32_B64 and S_FLBIT_I32_B64 are not currently supported by the DAG ISel. ctlz/cttz with i64 input are split into two 32bit instructions. Nevertheless, they already have the patterns and were equipped with the divergence predicates to make sure they will be selected correctly when enabled. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D116044
65 lines
2.5 KiB
LLVM
65 lines
2.5 KiB
LLVM
; RUN: llc -march=amdgcn -stop-after=amdgpu-isel < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: name: s_ctlz_i32
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; GCN: S_FLBIT_I32_B32
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define amdgpu_kernel void @s_ctlz_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
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%ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone
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store i32 %ctlz, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: name: v_ctlz_i32
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; GCN: V_FFBH_U32_e64
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define amdgpu_kernel void @v_ctlz_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
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%val = load i32, i32 addrspace(1)* %in.gep, align 4
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%ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 false) nounwind readnone
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store i32 %ctlz, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: name: s_cttz_i32
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; GCN: S_FF1_I32_B32
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define amdgpu_kernel void @s_cttz_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
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%cttz = call i32 @llvm.cttz.i32(i32 %val, i1 false) nounwind readnone
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store i32 %cttz, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: name: v_cttz_i32
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; GCN: V_FFBL_B32_e64
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define amdgpu_kernel void @v_cttz_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
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%val = load i32, i32 addrspace(1)* %in.gep, align 4
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%cttz = call i32 @llvm.cttz.i32(i32 %val, i1 false) nounwind readnone
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store i32 %cttz, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: name: s_flbit
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; GCN: S_FLBIT_I32
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define amdgpu_kernel void @s_flbit(i32 addrspace(1)* noalias %out, i32 %val) #0 {
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%r = call i32 @llvm.amdgcn.sffbh.i32(i32 %val)
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store i32 %r, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: name: v_flbit
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; GCN: V_FFBH_I32_e64
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define amdgpu_kernel void @v_flbit(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i32, i32 addrspace(1)* %valptr, i32 %tid
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%val = load i32, i32 addrspace(1)* %in.gep, align 4
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%r = call i32 @llvm.amdgcn.sffbh.i32(i32 %val)
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store i32 %r, i32 addrspace(1)* %out, align 4
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ret void
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}
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declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
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declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone
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declare i32 @llvm.amdgcn.sffbh.i32(i32)
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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