llvm-project/llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll
Venkata Ramanaiah Nalamothu 04fff547e2 [AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
Currently the return address ABI registers s[30:31], which fall in the call
clobbered register range, are added as a live-in on the function entry to
preserve its value when we have calls so that it gets saved and restored
around the calls.

But the DWARF unwind information (CFI) needs to track where the return address
resides in a frame and the above approach makes it difficult to track the
return address when the CFI information is emitted during the frame lowering,
due to the involvment of understanding the control flow.

This patch moves the return address ABI registers s[30:31] into callee saved
registers range and stops adding live-in for return address registers, so that
the CFI machinery will know where the return address resides when CSR
save/restore happen during the frame lowering.

And doing the above poses an issue that now the return instruction uses undefined
register `sgpr30_sgpr31`. This is resolved by hiding the return address register
use by the return instruction through the `SI_RETURN` pseudo instruction, which
doesn't take any input operands, until the `SI_RETURN` pseudo gets lowered to the
`S_SETPC_B64_return` during the `expandPostRAPseudo()`.

As an added benefit, this patch simplifies overall return instruction handling.

Note: The AMDGPU CFI changes are there only in the downstream code and another
version of this patch will be posted for review for the downstream code.

Reviewed By: arsenm, ronlieb

Differential Revision: https://reviews.llvm.org/D114652
2022-03-09 12:18:02 +05:30

46 lines
2.0 KiB
LLVM

; RUN: llc -march=amdgcn -mcpu=gfx900 -stop-after=prologepilog -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; It is a small loop test that iterates over the array member of the structure argument passed byval to the function.
; The loop code will keep the prologue and epilogue blocks apart.
; The test is primarily to check the temp register used to preserve the earlier FP value
; is live-in at every BB in the function.
%struct.Data = type { [20 x i32] }
define i32 @fp_save_restore_in_temp_sgpr(%struct.Data addrspace(5)* nocapture readonly byval(%struct.Data) align 4 %arg) #0 {
; GCN-LABEL: name: fp_save_restore_in_temp_sgpr
; GCN: bb.0.begin:
; GCN: liveins: $sgpr11
; GCN: $sgpr11 = frame-setup COPY $sgpr33
; GCN: $sgpr33 = frame-setup COPY $sgpr32
; GCN: bb.1.lp_end:
; GCN: liveins: $sgpr10, $sgpr11, $vgpr1, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9
; GCN: bb.2.lp_begin:
; GCN: liveins: $sgpr10, $sgpr11, $vgpr1, $sgpr4_sgpr5, $sgpr6_sgpr7
; GCN: bb.3.Flow:
; GCN: liveins: $sgpr10, $sgpr11, $vgpr0, $vgpr1, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9
; GCN: bb.4.end:
; GCN: liveins: $sgpr11, $vgpr0, $sgpr4_sgpr5
; GCN: $sgpr33 = frame-destroy COPY $sgpr11
begin:
br label %lp_begin
lp_end: ; preds = %lp_begin
%cur_idx = add nuw nsw i32 %idx, 1
%lp_term_cond = icmp eq i32 %cur_idx, 20
br i1 %lp_term_cond, label %end, label %lp_begin
lp_begin: ; preds = %lp_end, %begin
%idx = phi i32 [ 0, %begin ], [ %cur_idx, %lp_end ]
%ptr = getelementptr inbounds %struct.Data, %struct.Data addrspace(5)* %arg, i32 0, i32 0, i32 %idx
%data = load i32, i32 addrspace(5)* %ptr, align 4
%data_cmp = icmp eq i32 %data, %idx
br i1 %data_cmp, label %lp_end, label %end
end: ; preds = %lp_end, %lp_begin
%ret_val = phi i32 [ 0, %lp_begin ], [ 1, %lp_end ]
ret i32 %ret_val
}
attributes #0 = { norecurse nounwind "frame-pointer"="all" }