0f20a35b9e
Summary: In general, we need queue_ptr for aperture bases and trap handling, and user SGPRs have to be set up to hold queue_ptr. In current implementation, user SGPRs are set up unnecessarily for some cases. If the target has aperture registers, queue_ptr is not needed to reference aperture bases. For trap handling, if target suppots getDoorbellID, queue_ptr is also not necessary. Futher, code object version 5 introduces new kernel ABI which passes queue_ptr as an implicit kernel argument, so user SGPRs are no longer necessary for queue_ptr. Based on the trap handling document: https://llvm.org/docs/AMDGPUUsage.html#amdgpu-trap-handler-for-amdhsa-os-v4-onwards-table, llvm.debugtrap does not need queue_ptr, we remove queue_ptr suport for llvm.debugtrap in the backend. Reviewers: sameerds, arsenm Fixes: SWDEV-307189 Differential Revision: https://reviews.llvm.org/D119762
115 lines
5.6 KiB
LLVM
115 lines
5.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=5 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 --amdhsa-code-object-version=5 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=5 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefixes=CHECK,GFX9 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=5 < %s | FileCheck --check-prefix=CHECK %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 --amdhsa-code-object-version=5 < %s | FileCheck --check-prefix=CHECK %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=5 < %s | FileCheck --check-prefixes=CHECK,GFX9 %s
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; On gfx8, the queue ptr is required for this addrspacecast.
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; CHECK: - .args:
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; PRE-GFX9: .offset: 208
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; PRE-GFX9-NEXT: .size: 8
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; PRE-GFX9-NEXT: .value_kind: hidden_queue_ptr
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; GFX9-NOT: .value_kind: hidden_queue_ptr
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; CHECK: .name: addrspacecast_requires_queue_ptr
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; CHECK: .symbol: addrspacecast_requires_queue_ptr.kd
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define amdgpu_kernel void @addrspacecast_requires_queue_ptr(i32 addrspace(5)* %ptr.private, i32 addrspace(3)* %ptr.local) {
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%flat.private = addrspacecast i32 addrspace(5)* %ptr.private to i32*
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%flat.local = addrspacecast i32 addrspace(3)* %ptr.local to i32*
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store volatile i32 1, i32* %flat.private
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store volatile i32 2, i32* %flat.local
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ret void
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}
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; CHECK: - .args:
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; CHECK: .value_kind: hidden_multigrid_sync_arg
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; PRE-GFX9: .offset: 200
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; PRE-GFX9-NEXT: .size: 4
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; PRE-GFX9-NEXT: .value_kind: hidden_private_base
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; PRE-GFX9-NEXT: .offset: 204
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; PRE-GFX9-NEXT: .size: 4
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; PRE-GFX9-NEXT: .value_kind: hidden_shared_base
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; GFX9-NOT: .value_kind: hidden_multigrid_sync_arg
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; GFX9-NOT: .value_kind: hidden_private_base
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; CKECK-NOT: .value_kind: hidden_queue_ptr
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; CHECK: .name: is_shared_requires_queue_ptr
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; CHECK: .symbol: is_shared_requires_queue_ptr.kd
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define amdgpu_kernel void @is_shared_requires_queue_ptr(i8* %ptr) {
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%is.shared = call i1 @llvm.amdgcn.is.shared(i8* %ptr)
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%zext = zext i1 %is.shared to i32
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store volatile i32 %zext, i32 addrspace(1)* undef
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ret void
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}
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; CHECK: - .args:
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; CHECK: .value_kind: hidden_multigrid_sync_arg
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; PRE-GFX9: .offset: 200
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; PRE-GFX9-NEXT: .size: 4
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; PRE-GFX9-NEXT: .value_kind: hidden_private_base
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; PRE-GFX9-NEXT: .offset: 204
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; PRE-GFX9-NEXT: .size: 4
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; PRE-GFX9-NEXT: .value_kind: hidden_shared_base
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; GFX9-NOT: .value_kind: hidden_private_base
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; GFX9-NOT: .value_kind: hidden_shared_base
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; CKECK-NOT: .value_kind: hidden_queue_ptr
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; CHECK: .name: is_private_requires_queue_ptr
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; CHECK: .symbol: is_private_requires_queue_ptr.kd
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define amdgpu_kernel void @is_private_requires_queue_ptr(i8* %ptr) {
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%is.private = call i1 @llvm.amdgcn.is.private(i8* %ptr)
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%zext = zext i1 %is.private to i32
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store volatile i32 %zext, i32 addrspace(1)* undef
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ret void
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}
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; CHECK: - .args:
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; CHECK: .value_kind: hidden_multigrid_sync_arg
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; PRE-GFX9: .offset: 192
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; PRE-GFX9-NEXT: .size: 4
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; PRE-GFX9-NEXT: .value_kind: hidden_private_base
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; PRE-GFX9-NEXT: .offset: 196
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; PRE-GFX9-NEXT: .size: 4
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; PRE-GFX9-NEXT: .value_kind: hidden_shared_base
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; PRE-GFX9-NEXT: .address_space: global
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; PRE-GFX9-NEXT: .offset: 200
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; PRE-GFX9-NEXT: .size: 8
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; PRE-GFX9-NEXT: .value_kind: hidden_queue_ptr
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; GFX9-NOT: .value_kind: hidden_private_base
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; GFX9-NOT: .value_kind: hidden_shared_base
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; GFX9-NOT: .value_kind: hidden_queue_ptr
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; CHECK: .name: trap_requires_queue_ptr
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; CHECK: .symbol: trap_requires_queue_ptr.kd
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define amdgpu_kernel void @trap_requires_queue_ptr() {
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call void @llvm.trap()
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unreachable
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}
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; CHECK: - .args:
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; CHECK: .offset: 208
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; CHECK-NEXT: .size: 8
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; CHECK-NEXT: .value_kind: hidden_queue_ptr
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; CHECK: .name: amdgcn_queue_ptr_requires_queue_ptr
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; CHECK: .symbol: amdgcn_queue_ptr_requires_queue_ptr.kd
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define amdgpu_kernel void @amdgcn_queue_ptr_requires_queue_ptr(i64 addrspace(1)* %ptr) {
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%queue.ptr = call i8 addrspace(4)* @llvm.amdgcn.queue.ptr()
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
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%dispatch.id = call i64 @llvm.amdgcn.dispatch.id()
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%queue.load = load volatile i8, i8 addrspace(4)* %queue.ptr
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%implicitarg.load = load volatile i8, i8 addrspace(4)* %implicitarg.ptr
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%dispatch.load = load volatile i8, i8 addrspace(4)* %dispatch.ptr
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store volatile i64 %dispatch.id, i64 addrspace(1)* %ptr
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ret void
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}
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declare noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr()
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declare noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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declare i64 @llvm.amdgcn.dispatch.id()
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declare noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
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declare i1 @llvm.amdgcn.is.shared(i8*)
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declare i1 @llvm.amdgcn.is.private(i8*)
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declare void @llvm.trap()
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declare void @llvm.debugtrap()
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