da067ed569
Using a BufferSize of one for memory ProcResources will result in better ILP since it more accurately models the dependencies between memory ops and their consumers on an in-order processor. After this change, the scheduler will treat the data edges from loads as blocking so that stalls are guaranteed when waiting for data to be retreaved from memory. Since we don't actually track waitcnt here, this should do a better job at modeling their behavior. Practically, this means that the scheduler will trigger the 'STALL' heuristic more often. This type of change needs to be evaluated experimentally. Preliminary results are positive. Fixes: SWDEV-282962 Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D114777
188 lines
8.9 KiB
LLVM
188 lines
8.9 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,VI-FLUSH %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -denormal-fp-math=ieee -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -denormal-fp-math=ieee -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,VI-DENORM %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX10,GFX10-FLUSH %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=ieee -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX10,GFX10-DENORM %s
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declare half @llvm.fmuladd.f16(half %a, half %b, half %c)
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declare <2 x half> @llvm.fmuladd.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c)
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; GCN-LABEL: {{^}}fmuladd_f16
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
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; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
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; SI: v_mac_f32_e32 v[[C_F32]], v[[A_F32]], v[[B_F32]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[C_F32]]
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; SI: buffer_store_short v[[R_F16]]
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; VI-FLUSH: v_mac_f16_e32 v[[C_F16]], v[[A_F16]], v[[B_F16]]
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; VI-FLUSH: buffer_store_short v[[C_F16]]
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; VI-DENORM: v_fma_f16 [[RESULT:v[0-9]+]], v[[A_F16]], v[[B_F16]], v[[C_F16]]
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; VI-DENORM: buffer_store_short [[RESULT]]
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; GFX10-FLUSH: v_mul_f16_e32 [[MUL:v[0-9]+]], v[[A_F16]], v[[B_F16]]
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; GFX10-FLUSH: v_add_f16_e32 [[ADD:v[0-9]+]], [[MUL]], v[[C_F16]]
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; GFX10-FLUSH: buffer_store_short [[ADD]]
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; GFX10-DENORM: v_fmac_f16_e32 v[[C_F16]], v[[A_F16]], v[[B_F16]]
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; GFX10-DENORM: buffer_store_short v[[C_F16]],
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; GCN: s_endpgm
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define amdgpu_kernel void @fmuladd_f16(
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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half addrspace(1)* %b,
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half addrspace(1)* %c) {
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%a.val = load half, half addrspace(1)* %a
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%b.val = load half, half addrspace(1)* %b
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%c.val = load half, half addrspace(1)* %c
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%r.val = call half @llvm.fmuladd.f16(half %a.val, half %b.val, half %c.val)
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}fmuladd_f16_imm_a
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; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
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; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
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; SI: v_mac_f32_e32 v[[C_F32]], 0x40400000, v[[B_F32]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[C_F32]]
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; SI: buffer_store_short v[[R_F16]]
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; VI-FLUSH: v_mac_f16_e32 v[[C_F16]], 0x4200, v[[B_F16]]
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; VI-FLUSH: buffer_store_short v[[C_F16]]
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; VI-DENORM: s_movk_i32 [[KA:s[0-9]+]], 0x4200
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; VI-DENORM: v_fma_f16 [[RESULT:v[0-9]+]], v[[B_F16]], [[KA]], v[[C_F16]]
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; VI-DENORM: buffer_store_short [[RESULT]]
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; GFX10-FLUSH: v_mul_f16_e32 [[MUL:v[0-9]+]], 0x4200, v[[B_F16]]
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; GFX10-FLUSH: v_add_f16_e32 [[ADD:v[0-9]+]], [[MUL]], v[[C_F16]]
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; GFX10-FLUSH: buffer_store_short [[ADD]]
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; GFX10-DENORM: v_fmac_f16_e32 v[[C_F16]], 0x4200, v[[B_F16]]
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; GFX10-DENORM: buffer_store_short v[[C_F16]],
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; GCN: s_endpgm
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define amdgpu_kernel void @fmuladd_f16_imm_a(
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half addrspace(1)* %r,
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half addrspace(1)* %b,
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half addrspace(1)* %c) {
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%b.val = load volatile half, half addrspace(1)* %b
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%c.val = load volatile half, half addrspace(1)* %c
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%r.val = call half @llvm.fmuladd.f16(half 3.0, half %b.val, half %c.val)
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}fmuladd_f16_imm_b
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
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; SI: v_mac_f32_e32 v[[C_F32]], 0x40400000, v[[A_F32]]
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; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[C_F32]]
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; SI: buffer_store_short v[[R_F16]]
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; VI-FLUSH: v_mac_f16_e32 v[[C_F16]], 0x4200, v[[A_F16]]
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; VI-FLUSH: buffer_store_short v[[C_F16]]
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; VI-DENORM: s_movk_i32 [[KA:s[0-9]+]], 0x4200
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; VI-DENORM: v_fma_f16 [[RESULT:v[0-9]+]], v[[A_F16]], [[KA]], v[[C_F16]]
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; VI-DENORM: buffer_store_short [[RESULT]]
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; GFX10-FLUSH: v_mul_f16_e32 [[MUL:v[0-9]+]], 0x4200, v[[A_F16]]
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; GFX10-FLUSH: v_add_f16_e32 [[ADD:v[0-9]+]], [[MUL]], v[[C_F16]]
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; GFX10-FLUSH: buffer_store_short [[ADD]]
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; GFX10-DENORM: v_fmac_f16_e32 v[[C_F16]], 0x4200, v[[A_F16]]
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; GFX10-DENORM: buffer_store_short v[[C_F16]],
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; GCN: s_endpgm
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define amdgpu_kernel void @fmuladd_f16_imm_b(
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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half addrspace(1)* %c) {
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%a.val = load volatile half, half addrspace(1)* %a
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%c.val = load volatile half, half addrspace(1)* %c
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%r.val = call half @llvm.fmuladd.f16(half %a.val, half 3.0, half %c.val)
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}fmuladd_v2f16
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; SI: buffer_load_dword v[[A_V2_F16:[0-9]+]]
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; SI: buffer_load_dword v[[B_V2_F16:[0-9]+]]
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; SI: buffer_load_dword v[[C_V2_F16:[0-9]+]]
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; VI-FLUSH: buffer_load_dword v[[A_V2_F16:[0-9]+]]
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; VI-FLUSH: buffer_load_dword v[[C_V2_F16:[0-9]+]]
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; VI-FLUSH: buffer_load_dword v[[B_V2_F16:[0-9]+]]
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; VI-DENORM: buffer_load_dword v[[A_V2_F16:[0-9]+]]
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; VI-DENORM: buffer_load_dword v[[B_V2_F16:[0-9]+]]
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; VI-DENORM: buffer_load_dword v[[C_V2_F16:[0-9]+]]
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; GFX10: buffer_load_dword v[[A_V2_F16:[0-9]+]]
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; GFX10: buffer_load_dword v[[B_V2_F16:[0-9]+]]
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; GFX10: buffer_load_dword v[[C_V2_F16:[0-9]+]]
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; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
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; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
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; SI: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]]
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; SI: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]]
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; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_0:[0-9]+]], v[[B_V2_F16]]
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; SI-DAG: v_cvt_f32_f16_e32 v[[C_F32_0:[0-9]+]], v[[C_V2_F16]]
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; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
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; SI-DAG: v_cvt_f32_f16_e32 v[[B_F32_1:[0-9]+]], v[[B_F16_1]]
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; SI-DAG: v_cvt_f32_f16_e32 v[[C_F32_1:[0-9]+]], v[[C_F16_1]]
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; SI-DAG: v_mac_f32_e32 v[[C_F32_0]], v[[A_F32_0]], v[[B_F32_0]]
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; SI-DAG: v_mac_f32_e32 v[[C_F32_1]], v[[A_F32_1]], v[[B_F32_1]]
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; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[C_F32_1]]
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; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_LO:[0-9]+]], v[[C_F32_0]]
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; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
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; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_LO]], v[[R_F16_HI]]
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; VI-FLUSH: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]]
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; VI-FLUSH-DAG: v_mac_f16_sdwa v[[C_F16_1]], v[[A_V2_F16]], v[[B_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI-FLUSH-DAG: v_mac_f16_e32 v[[C_V2_F16]], v[[A_V2_F16]], v[[B_V2_F16]]
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; VI-FLUSH-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[C_F16_1]]
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; VI-FLUSH-NOT: v_and_b32
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; VI-FLUSH: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[C_V2_F16]], v[[R_F16_HI]]
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; VI-DENORM-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
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; VI-DENORM-DAG: v_lshrrev_b32_e32 v[[B_F16_1:[0-9]+]], 16, v[[B_V2_F16]]
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; VI-DENORM-DAG: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]]
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; VI-DENORM-DAG: v_fma_f16 v[[RES0:[0-9]+]], v[[C_V2_F16]], v[[B_V2_F16]], v[[A_V2_F16]]
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; VI-DENORM-DAG: v_fma_f16 v[[RES1:[0-9]+]], v[[C_F16_1]], v[[B_F16_1]], v[[A_F16_1]]
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; VI-DENORM-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[RES1]]
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; VI-DENORM-NOT: v_and_b32
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; VI-DENORM: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[RES0]], v[[R_F16_HI]]
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; GFX10-FLUSH: v_pk_mul_f16 [[MUL:v[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]]
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; GFX10-FLUSH: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], [[MUL]], v[[C_V2_F16]]
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; GFX10-DENORM: v_pk_fma_f16 v[[R_V2_F16:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]], v[[C_V2_F16]]
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; GCN: buffer_store_dword v[[R_V2_F16]]
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define amdgpu_kernel void @fmuladd_v2f16(
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<2 x half> addrspace(1)* %r,
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<2 x half> addrspace(1)* %a,
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<2 x half> addrspace(1)* %b,
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<2 x half> addrspace(1)* %c) {
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%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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%b.val = load <2 x half>, <2 x half> addrspace(1)* %b
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%c.val = load <2 x half>, <2 x half> addrspace(1)* %c
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%r.val = call <2 x half> @llvm.fmuladd.v2f16(<2 x half> %a.val, <2 x half> %b.val, <2 x half> %c.val)
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store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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ret void
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}
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