0be6fd44f3
SDNodes with different target flags may now be folded together rightfully resulting in the assertion in the refineAlignment. Folding nodes with different target flags may result in the wrong load instructions produced at least on the AMDGPU. Fixes: SWDEV-326805 Differential Revision: https://reviews.llvm.org/D121335
27 lines
1.1 KiB
LLVM
27 lines
1.1 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefix=GCN %s
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; This is used to crash due to mismatch of MMO target flags when folding
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; a LOAD SDNodes with different flags.
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; GCN-LABEL: {{^}}test_load_folding_mmo_flags:
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; GCN: global_load_dwordx2
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define amdgpu_kernel void @test_load_folding_mmo_flags(<2 x float> addrspace(1)* %arg) {
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entry:
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%arrayidx = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %arg, i32 %id
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%i1 = bitcast <2 x float> addrspace(1)* %arrayidx to i64 addrspace(1)*
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%i2 = getelementptr <2 x float>, <2 x float> addrspace(1)* %arrayidx, i64 0, i32 0
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%i3 = load float, float addrspace(1)* %i2, align 4
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%idx = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %arrayidx, i64 0, i32 1
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%i4 = load float, float addrspace(1)* %idx, align 4
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%i5 = load i64, i64 addrspace(1)* %i1, align 4, !amdgpu.noclobber !0
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store i64 %i5, i64 addrspace(1)* undef, align 4
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%mul = fmul float %i3, %i4
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store float %mul, float addrspace(1)* undef, align 4
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unreachable
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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!0 = !{}
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