adfd12e6d1
As an extension to D107866, this adds store(fptosisat(..)) patterns, similar to the existing fptosi patterns, to prevent unnecessarily moving into gpr regs where we can use fp stores directly. Differential Revision: https://reviews.llvm.org/D108378
272 lines
8.0 KiB
LLVM
272 lines
8.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv6-none-eabi -float-abi=soft %s -o - | FileCheck %s --check-prefixes=SOFT
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; RUN: llc -mtriple=thumbv7-none-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefixes=VFP,VFP2
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; RUN: llc -mtriple=thumbv8.1m.main-eabi -mattr=+fullfp16,+fp64 %s -o - | FileCheck %s --check-prefixes=VFP,FP16
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declare i32 @llvm.fptosi.sat.i32.f64(double)
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declare i32 @llvm.fptosi.sat.i32.f32(float)
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declare i32 @llvm.fptoui.sat.i32.f64(double)
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declare i32 @llvm.fptoui.sat.i32.f32(float)
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define void @test_signed_i32_f32(i32* %d, float %f) nounwind {
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; SOFT-LABEL: test_signed_i32_f32:
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; SOFT: @ %bb.0:
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; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
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; SOFT-NEXT: push {r4, r5, r6, r7, lr}
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; SOFT-NEXT: .pad #4
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; SOFT-NEXT: sub sp, #4
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; SOFT-NEXT: mov r5, r1
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; SOFT-NEXT: mov r4, r0
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; SOFT-NEXT: movs r0, #207
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; SOFT-NEXT: lsls r1, r0, #24
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; SOFT-NEXT: mov r0, r5
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; SOFT-NEXT: bl __aeabi_fcmpge
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; SOFT-NEXT: mov r7, r0
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; SOFT-NEXT: mov r0, r5
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; SOFT-NEXT: bl __aeabi_f2iz
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; SOFT-NEXT: cmp r7, #0
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; SOFT-NEXT: beq .LBB0_2
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; SOFT-NEXT: @ %bb.1:
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; SOFT-NEXT: mov r6, r0
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; SOFT-NEXT: b .LBB0_3
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; SOFT-NEXT: .LBB0_2:
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; SOFT-NEXT: movs r0, #1
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; SOFT-NEXT: lsls r6, r0, #31
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; SOFT-NEXT: .LBB0_3:
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; SOFT-NEXT: ldr r1, .LCPI0_0
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; SOFT-NEXT: mov r0, r5
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; SOFT-NEXT: bl __aeabi_fcmpgt
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; SOFT-NEXT: cmp r0, #0
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; SOFT-NEXT: beq .LBB0_5
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; SOFT-NEXT: @ %bb.4:
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; SOFT-NEXT: ldr r6, .LCPI0_1
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; SOFT-NEXT: .LBB0_5:
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; SOFT-NEXT: mov r0, r5
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; SOFT-NEXT: mov r1, r5
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; SOFT-NEXT: bl __aeabi_fcmpun
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; SOFT-NEXT: cmp r0, #0
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; SOFT-NEXT: beq .LBB0_7
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; SOFT-NEXT: @ %bb.6:
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; SOFT-NEXT: movs r6, #0
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; SOFT-NEXT: .LBB0_7:
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; SOFT-NEXT: str r6, [r4]
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; SOFT-NEXT: add sp, #4
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; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
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; SOFT-NEXT: .p2align 2
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; SOFT-NEXT: @ %bb.8:
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; SOFT-NEXT: .LCPI0_0:
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; SOFT-NEXT: .long 1325400063 @ 0x4effffff
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; SOFT-NEXT: .LCPI0_1:
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; SOFT-NEXT: .long 2147483647 @ 0x7fffffff
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;
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; VFP-LABEL: test_signed_i32_f32:
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; VFP: @ %bb.0:
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; VFP-NEXT: vmov s0, r1
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; VFP-NEXT: vcvt.s32.f32 s0, s0
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; VFP-NEXT: vstr s0, [r0]
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; VFP-NEXT: bx lr
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%r = call i32 @llvm.fptosi.sat.i32.f32(float %f)
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store i32 %r, i32* %d, align 4
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ret void
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}
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define void @test_signed_i32_f64(i32* %d, double %f) nounwind {
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; SOFT-LABEL: test_signed_i32_f64:
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; SOFT: @ %bb.0:
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; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
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; SOFT-NEXT: push {r4, r5, r6, r7, lr}
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; SOFT-NEXT: .pad #12
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; SOFT-NEXT: sub sp, #12
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; SOFT-NEXT: mov r5, r3
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; SOFT-NEXT: mov r6, r2
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; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill
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; SOFT-NEXT: ldr r2, .LCPI1_0
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; SOFT-NEXT: ldr r3, .LCPI1_1
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; SOFT-NEXT: mov r0, r6
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; SOFT-NEXT: mov r1, r5
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; SOFT-NEXT: bl __aeabi_dcmpgt
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; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill
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; SOFT-NEXT: movs r7, #0
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; SOFT-NEXT: ldr r3, .LCPI1_2
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; SOFT-NEXT: mov r0, r6
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; SOFT-NEXT: mov r1, r5
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; SOFT-NEXT: mov r2, r7
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; SOFT-NEXT: bl __aeabi_dcmpge
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; SOFT-NEXT: mov r4, r0
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; SOFT-NEXT: mov r0, r6
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; SOFT-NEXT: mov r1, r5
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; SOFT-NEXT: bl __aeabi_d2iz
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; SOFT-NEXT: cmp r4, #0
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; SOFT-NEXT: bne .LBB1_2
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; SOFT-NEXT: @ %bb.1:
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; SOFT-NEXT: movs r0, #1
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; SOFT-NEXT: lsls r0, r0, #31
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; SOFT-NEXT: .LBB1_2:
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; SOFT-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
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; SOFT-NEXT: cmp r1, #0
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; SOFT-NEXT: bne .LBB1_4
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; SOFT-NEXT: @ %bb.3:
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; SOFT-NEXT: mov r4, r0
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; SOFT-NEXT: b .LBB1_5
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; SOFT-NEXT: .LBB1_4:
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; SOFT-NEXT: ldr r4, .LCPI1_3
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; SOFT-NEXT: .LBB1_5:
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; SOFT-NEXT: mov r0, r6
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; SOFT-NEXT: mov r1, r5
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; SOFT-NEXT: mov r2, r6
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; SOFT-NEXT: mov r3, r5
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; SOFT-NEXT: bl __aeabi_dcmpun
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; SOFT-NEXT: cmp r0, #0
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; SOFT-NEXT: bne .LBB1_7
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; SOFT-NEXT: @ %bb.6:
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; SOFT-NEXT: mov r7, r4
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; SOFT-NEXT: .LBB1_7:
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; SOFT-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
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; SOFT-NEXT: str r7, [r0]
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; SOFT-NEXT: add sp, #12
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; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
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; SOFT-NEXT: .p2align 2
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; SOFT-NEXT: @ %bb.8:
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; SOFT-NEXT: .LCPI1_0:
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; SOFT-NEXT: .long 4290772992 @ 0xffc00000
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; SOFT-NEXT: .LCPI1_1:
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; SOFT-NEXT: .long 1105199103 @ 0x41dfffff
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; SOFT-NEXT: .LCPI1_2:
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; SOFT-NEXT: .long 3252682752 @ 0xc1e00000
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; SOFT-NEXT: .LCPI1_3:
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; SOFT-NEXT: .long 2147483647 @ 0x7fffffff
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;
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; VFP2-LABEL: test_signed_i32_f64:
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; VFP2: @ %bb.0:
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; VFP2-NEXT: vmov d16, r2, r3
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; VFP2-NEXT: vcvt.s32.f64 s0, d16
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; VFP2-NEXT: vstr s0, [r0]
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; VFP2-NEXT: bx lr
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;
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; FP16-LABEL: test_signed_i32_f64:
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; FP16: @ %bb.0:
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; FP16-NEXT: vmov d0, r2, r3
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; FP16-NEXT: vcvt.s32.f64 s0, d0
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; FP16-NEXT: vstr s0, [r0]
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; FP16-NEXT: bx lr
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%r = call i32 @llvm.fptosi.sat.i32.f64(double %f)
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store i32 %r, i32* %d, align 4
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ret void
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}
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define void @test_unsigned_i32_f32(i32* %d, float %f) nounwind {
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; SOFT-LABEL: test_unsigned_i32_f32:
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; SOFT: @ %bb.0:
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; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
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; SOFT-NEXT: push {r4, r5, r6, r7, lr}
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; SOFT-NEXT: .pad #4
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; SOFT-NEXT: sub sp, #4
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; SOFT-NEXT: mov r7, r1
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; SOFT-NEXT: str r0, [sp] @ 4-byte Spill
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; SOFT-NEXT: ldr r1, .LCPI2_0
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; SOFT-NEXT: mov r0, r7
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; SOFT-NEXT: bl __aeabi_fcmpgt
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; SOFT-NEXT: mov r6, r0
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; SOFT-NEXT: movs r5, #0
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; SOFT-NEXT: mov r0, r7
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; SOFT-NEXT: mov r1, r5
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; SOFT-NEXT: bl __aeabi_fcmpge
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; SOFT-NEXT: mov r4, r0
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; SOFT-NEXT: mov r0, r7
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; SOFT-NEXT: bl __aeabi_f2uiz
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; SOFT-NEXT: cmp r4, #0
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; SOFT-NEXT: bne .LBB2_2
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; SOFT-NEXT: @ %bb.1:
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; SOFT-NEXT: mov r0, r4
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; SOFT-NEXT: .LBB2_2:
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; SOFT-NEXT: cmp r6, #0
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; SOFT-NEXT: beq .LBB2_4
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; SOFT-NEXT: @ %bb.3:
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; SOFT-NEXT: mvns r0, r5
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; SOFT-NEXT: .LBB2_4:
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; SOFT-NEXT: ldr r1, [sp] @ 4-byte Reload
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; SOFT-NEXT: str r0, [r1]
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; SOFT-NEXT: add sp, #4
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; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
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; SOFT-NEXT: .p2align 2
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; SOFT-NEXT: @ %bb.5:
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; SOFT-NEXT: .LCPI2_0:
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; SOFT-NEXT: .long 1333788671 @ 0x4f7fffff
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;
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; VFP-LABEL: test_unsigned_i32_f32:
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; VFP: @ %bb.0:
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; VFP-NEXT: vmov s0, r1
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; VFP-NEXT: vcvt.u32.f32 s0, s0
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; VFP-NEXT: vstr s0, [r0]
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; VFP-NEXT: bx lr
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%r = call i32 @llvm.fptoui.sat.i32.f32(float %f)
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store i32 %r, i32* %d, align 4
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ret void
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}
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define void @test_unsigned_i32_f64(i32* %d, double %f) nounwind {
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; SOFT-LABEL: test_unsigned_i32_f64:
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; SOFT: @ %bb.0:
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; SOFT-NEXT: .save {r4, r5, r6, r7, lr}
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; SOFT-NEXT: push {r4, r5, r6, r7, lr}
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; SOFT-NEXT: .pad #12
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; SOFT-NEXT: sub sp, #12
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; SOFT-NEXT: mov r5, r3
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; SOFT-NEXT: mov r4, r2
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; SOFT-NEXT: str r0, [sp, #8] @ 4-byte Spill
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; SOFT-NEXT: ldr r2, .LCPI3_0
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; SOFT-NEXT: ldr r3, .LCPI3_1
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; SOFT-NEXT: mov r0, r4
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; SOFT-NEXT: mov r1, r5
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; SOFT-NEXT: bl __aeabi_dcmpgt
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; SOFT-NEXT: str r0, [sp, #4] @ 4-byte Spill
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; SOFT-NEXT: movs r6, #0
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; SOFT-NEXT: mov r0, r4
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; SOFT-NEXT: mov r1, r5
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; SOFT-NEXT: mov r2, r6
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; SOFT-NEXT: mov r3, r6
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; SOFT-NEXT: bl __aeabi_dcmpge
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; SOFT-NEXT: mov r7, r0
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; SOFT-NEXT: mov r0, r4
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; SOFT-NEXT: mov r1, r5
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; SOFT-NEXT: bl __aeabi_d2uiz
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; SOFT-NEXT: cmp r7, #0
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; SOFT-NEXT: bne .LBB3_2
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; SOFT-NEXT: @ %bb.1:
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; SOFT-NEXT: mov r0, r7
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; SOFT-NEXT: .LBB3_2:
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; SOFT-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
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; SOFT-NEXT: cmp r1, #0
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; SOFT-NEXT: beq .LBB3_4
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; SOFT-NEXT: @ %bb.3:
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; SOFT-NEXT: mvns r0, r6
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; SOFT-NEXT: .LBB3_4:
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; SOFT-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
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; SOFT-NEXT: str r0, [r1]
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; SOFT-NEXT: add sp, #12
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; SOFT-NEXT: pop {r4, r5, r6, r7, pc}
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; SOFT-NEXT: .p2align 2
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; SOFT-NEXT: @ %bb.5:
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; SOFT-NEXT: .LCPI3_0:
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; SOFT-NEXT: .long 4292870144 @ 0xffe00000
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; SOFT-NEXT: .LCPI3_1:
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; SOFT-NEXT: .long 1106247679 @ 0x41efffff
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;
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; VFP2-LABEL: test_unsigned_i32_f64:
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; VFP2: @ %bb.0:
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; VFP2-NEXT: vmov d16, r2, r3
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; VFP2-NEXT: vcvt.u32.f64 s0, d16
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; VFP2-NEXT: vstr s0, [r0]
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; VFP2-NEXT: bx lr
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;
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; FP16-LABEL: test_unsigned_i32_f64:
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; FP16: @ %bb.0:
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; FP16-NEXT: vmov d0, r2, r3
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; FP16-NEXT: vcvt.u32.f64 s0, d0
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; FP16-NEXT: vstr s0, [r0]
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; FP16-NEXT: bx lr
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%r = call i32 @llvm.fptoui.sat.i32.f64(double %f)
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store i32 %r, i32* %d, align 4
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ret void
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}
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