2b1c6df5a6
For code below:
{
r7 = addasl(r3,r0,#2)
r8 = addasl(r3,r2,#2)
r5 = memw(r3+r0<<#2)
r6 = memw(r3+r2<<#2)
}
{
p1 = cmp.gtu(r6,r5)
if (p1.new) memw(r8+#0) = r5
if (p1.new) memw(r7+#0) = r6
}
{
r0 = mux(p1,r2,r4)
}
In packetizer, a new packet is created for the cmp instruction since
there arent enough resources in previous packet. Also it is determined
that the cmp stalls by 2 cycles since it depends on the prior load of r5.
In current packetizer implementation, the predicated store is evaluated
for whether it can go in the same packet as compare, and since the compare
stalls, the stall of the predicated store does not matter and it can go in
the same packet as the cmp. However the predicated store will stall for
more cycles because of its dependence on the addasl instruction and to
avoid that stall we can put it in a new packet.
Improve the packetizer to check if an instruction being added to packet
will stall longer than instruction already in packet and if so create a
new packet.
65 lines
2.4 KiB
LLVM
65 lines
2.4 KiB
LLVM
; RUN: llc -march=hexagon -O3 < %s | FileCheck %s
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; if instruction being considered for addition to packet has higher latency,
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; end existing packet and start a new one.
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; CHECK: .LBB0_4:
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; CHECK: p{{[0-3]+}} = cmp.gtu(r{{[0-9]+}},r{{[0-9]+}})
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; CHECK-NEXT: }
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@array = external dso_local local_unnamed_addr global i32*, align 4
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; Function Attrs: nofree norecurse nounwind
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define dso_local void @NumSift(i32 %i, i32 %j) local_unnamed_addr #0 {
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entry:
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%add36 = shl i32 %i, 1
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%cmp.not37 = icmp ugt i32 %add36, %j
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br i1 %cmp.not37, label %while.end, label %while.body.lr.ph
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while.body.lr.ph: ; preds = %entry
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%0 = load i32*, i32** @array, align 4
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%add16 = add i32 %j, 1
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br label %while.body
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while.body: ; preds = %while.body.lr.ph, %if.end17
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%add39 = phi i32 [ %add36, %while.body.lr.ph ], [ %add, %if.end17 ]
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%i.addr.038 = phi i32 [ %i, %while.body.lr.ph ], [ %i.addr.1, %if.end17 ]
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%cmp2 = icmp ult i32 %add39, %j
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br i1 %cmp2, label %if.then, label %if.end7
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if.then: ; preds = %while.body
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%arrayidx = getelementptr inbounds i32, i32* %0, i32 %add39
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%1 = load i32, i32* %arrayidx, align 4
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%add3 = or i32 %add39, 1
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%arrayidx4 = getelementptr inbounds i32, i32* %0, i32 %add3
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%2 = load i32, i32* %arrayidx4, align 4
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%cmp5 = icmp ult i32 %1, %2
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%spec.select = select i1 %cmp5, i32 %add3, i32 %add39
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br label %if.end7
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if.end7: ; preds = %if.then, %while.body
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%k.0 = phi i32 [ %add39, %while.body ], [ %spec.select, %if.then ]
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%arrayidx8 = getelementptr inbounds i32, i32* %0, i32 %i.addr.038
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%3 = load i32, i32* %arrayidx8, align 4
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%arrayidx9 = getelementptr inbounds i32, i32* %0, i32 %k.0
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%4 = load i32, i32* %arrayidx9, align 4
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%cmp10 = icmp ult i32 %3, %4
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br i1 %cmp10, label %if.then11, label %if.end17
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if.then11: ; preds = %if.end7
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store i32 %3, i32* %arrayidx9, align 4
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store i32 %4, i32* %arrayidx8, align 4
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br label %if.end17
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if.end17: ; preds = %if.end7, %if.then11
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%i.addr.1 = phi i32 [ %k.0, %if.then11 ], [ %add16, %if.end7 ]
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%add = shl i32 %i.addr.1, 1
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%cmp.not = icmp ugt i32 %add, %j
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br i1 %cmp.not, label %while.end, label %while.body
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while.end: ; preds = %if.end17, %entry
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ret void
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}
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attributes #0 = { "target-cpu"="hexagonv65" }
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