d391e4fe84
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth. Helps prevent future scheduler model mismatches like those that were only addressed in D44687. Differential Revision: https://reviews.llvm.org/D113302
25 lines
467 B
YAML
25 lines
467 B
YAML
# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
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--- |
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define i32 @test(i32* %a) {
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entry:
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%b = load i32, i32* %a
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ret i32 %b
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}
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...
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---
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name: test
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tracksRegLiveness: true
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liveins:
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- { reg: '$rdi' }
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body: |
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bb.0.entry:
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liveins: $rdi
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; CHECK: [[@LINE+1]]:53: expected an atomic scope, ordering or a size specification
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$eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load from %ir.a)
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RET64 $eax
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...
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