fae05692a3
This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
95 lines
3.2 KiB
YAML
95 lines
3.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP32
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP64
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--- |
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define void @load_i32(i32* %ptr) {entry: ret void}
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define void @load_float(float* %ptr) {entry: ret void}
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define void @load_double(double* %ptr) {entry: ret void}
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...
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---
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name: load_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32FP32-LABEL: name: load_i32
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; MIPS32FP32: liveins: $a0
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; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load (s32) from %ir.ptr)
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; MIPS32FP32: $v0 = COPY [[LW]]
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; MIPS32FP32: RetRA implicit $v0
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; MIPS32FP64-LABEL: name: load_i32
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; MIPS32FP64: liveins: $a0
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; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load (s32) from %ir.ptr)
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; MIPS32FP64: $v0 = COPY [[LW]]
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; MIPS32FP64: RetRA implicit $v0
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%0:gprb(p0) = COPY $a0
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%1:gprb(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.ptr)
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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---
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name: load_float
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32FP32-LABEL: name: load_float
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; MIPS32FP32: liveins: $a0
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; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP32: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[COPY]], 0 :: (load (s32) from %ir.ptr)
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; MIPS32FP32: $f0 = COPY [[LWC1_]]
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; MIPS32FP32: RetRA implicit $f0
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; MIPS32FP64-LABEL: name: load_float
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; MIPS32FP64: liveins: $a0
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; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP64: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[COPY]], 0 :: (load (s32) from %ir.ptr)
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; MIPS32FP64: $f0 = COPY [[LWC1_]]
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; MIPS32FP64: RetRA implicit $f0
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%0:gprb(p0) = COPY $a0
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%1:fprb(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.ptr)
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$f0 = COPY %1(s32)
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RetRA implicit $f0
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...
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---
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name: load_double
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32FP32-LABEL: name: load_double
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; MIPS32FP32: liveins: $a0
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; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP32: [[LDC1_:%[0-9]+]]:afgr64 = LDC1 [[COPY]], 0 :: (load (s64) from %ir.ptr)
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; MIPS32FP32: $d0 = COPY [[LDC1_]]
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; MIPS32FP32: RetRA implicit $d0
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; MIPS32FP64-LABEL: name: load_double
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; MIPS32FP64: liveins: $a0
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; MIPS32FP64: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32FP64: [[LDC164_:%[0-9]+]]:fgr64 = LDC164 [[COPY]], 0 :: (load (s64) from %ir.ptr)
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; MIPS32FP64: $d0 = COPY [[LDC164_]]
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; MIPS32FP64: RetRA implicit $d0
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%0:gprb(p0) = COPY $a0
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%1:fprb(s64) = G_LOAD %0(p0) :: (load (s64) from %ir.ptr)
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$d0 = COPY %1(s64)
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RetRA implicit $d0
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...
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