llvm-project/llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee-split.ll
Matt Arsenault fae05692a3 CodeGen: Print/parse LLTs in MachineMemOperands
This will currently accept the old number of bytes syntax, and convert
it to a scalar. This should be removed in the near future (I think I
converted all of the tests already, but likely missed a few).

Not sure what the exact syntax and policy should be. We can continue
printing the number of bytes for non-generic instructions to avoid
test churn and only allow non-scalar types for generic instructions.

This will currently print the LLT in parentheses, but accept parsing
the existing integers and implicitly converting to scalar. The
parentheses are a bit ugly, but the parser logic seems unable to deal
without either parentheses or some keyword to indicate the start of a
type.
2021-06-30 16:54:13 -04:00

50 lines
2.1 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -verify-machineinstrs -stop-before=ppc-vsx-copy -vec-extabi \
; RUN: -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s | \
; RUN: FileCheck %s
;; Testing a variadic callee where a vector argument passed through ellipsis
;; is passed partially in registers and on the stack. The 3 fixed double
;; arguments shadow r3-r8, and a vector int <4 x i32> is passed in R9/R10 and
;; on the stack starting at the shadow of R9.
define <4 x i32> @split_spill(double %d1, double %d2, double %d3, ...) {
; CHECK-LABEL: name: split_spill
; CHECK: bb.0.entry:
; CHECK: liveins: $r9, $r10
; CHECK: [[COPY:%[0-9]+]]:gprc = COPY $r10
; CHECK: [[COPY1:%[0-9]+]]:gprc = COPY $r9
; CHECK: STW [[COPY1]], 0, %fixed-stack.0 :: (store (s32) into %fixed-stack.0, align 16)
; CHECK: STW [[COPY]], 4, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 4)
; CHECK: LIFETIME_START %stack.0.arg_list
; CHECK: [[ADDI:%[0-9]+]]:gprc = ADDI %fixed-stack.0, 0
; CHECK: [[LXVW4X:%[0-9]+]]:vsrc = LXVW4X $zero, killed [[ADDI]] :: (load (s128) from %ir.4)
; CHECK: LIFETIME_END %stack.0.arg_list
; CHECK: $v2 = COPY [[LXVW4X]]
; CHECK: BLR implicit $lr, implicit $rm, implicit $v2
entry:
%arg_list = alloca i8*, align 4
%0 = bitcast i8** %arg_list to i8*
call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0)
call void @llvm.va_start(i8* nonnull %0)
%argp.cur = load i8*, i8** %arg_list, align 4
%1 = ptrtoint i8* %argp.cur to i32
%2 = add i32 %1, 15
%3 = and i32 %2, -16
%argp.cur.aligned = inttoptr i32 %3 to i8*
%argp.next = getelementptr inbounds i8, i8* %argp.cur.aligned, i32 16
store i8* %argp.next, i8** %arg_list, align 4
%4 = inttoptr i32 %3 to <4 x i32>*
%5 = load <4 x i32>, <4 x i32>* %4, align 16
call void @llvm.va_end(i8* nonnull %0)
call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %0)
ret <4 x i32> %5
}
declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
declare void @llvm.va_start(i8*)
declare void @llvm.va_end(i8*)
declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)