e68257fcee
Modified DAGCombiner to pass the shift the bittest input and the shift amount to hasBitTest. This matches the other call to hasBitTest in TargetLowering.h This is an alternative to D122454. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D122458
190 lines
4.7 KiB
LLVM
190 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64ZBS
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define signext i32 @bittest_7_i32(i32 signext %a) nounwind {
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; RV64I-LABEL: bittest_7_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 128
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; RV64I-NEXT: seqz a0, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_7_i32:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: andi a0, a0, 128
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; RV64ZBS-NEXT: seqz a0, a0
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; RV64ZBS-NEXT: ret
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%shr = lshr i32 %a, 7
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%not = xor i32 %shr, -1
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%and = and i32 %not, 1
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ret i32 %and
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}
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define signext i32 @bittest_10_i32(i32 signext %a) nounwind {
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; RV64I-LABEL: bittest_10_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 1024
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; RV64I-NEXT: seqz a0, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_10_i32:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: andi a0, a0, 1024
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; RV64ZBS-NEXT: seqz a0, a0
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; RV64ZBS-NEXT: ret
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%shr = lshr i32 %a, 10
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%not = xor i32 %shr, -1
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%and = and i32 %not, 1
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ret i32 %and
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}
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define signext i32 @bittest_11_i32(i32 signext %a) nounwind {
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; RV64I-LABEL: bittest_11_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srli a0, a0, 11
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; RV64I-NEXT: not a0, a0
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_11_i32:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: bexti a0, a0, 11
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; RV64ZBS-NEXT: xori a0, a0, 1
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; RV64ZBS-NEXT: ret
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%shr = lshr i32 %a, 11
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%not = xor i32 %shr, -1
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%and = and i32 %not, 1
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ret i32 %and
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}
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define signext i32 @bittest_31_i32(i32 signext %a) nounwind {
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; RV64I-LABEL: bittest_31_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: not a0, a0
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; RV64I-NEXT: srliw a0, a0, 31
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; RV64I-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_31_i32:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: not a0, a0
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; RV64ZBS-NEXT: srliw a0, a0, 31
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; RV64ZBS-NEXT: ret
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%shr = lshr i32 %a, 31
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%not = xor i32 %shr, -1
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%and = and i32 %not, 1
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ret i32 %and
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}
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define i64 @bittest_7_i64(i64 %a) nounwind {
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; RV64I-LABEL: bittest_7_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 128
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; RV64I-NEXT: seqz a0, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_7_i64:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: andi a0, a0, 128
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; RV64ZBS-NEXT: seqz a0, a0
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; RV64ZBS-NEXT: ret
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%shr = lshr i64 %a, 7
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%not = xor i64 %shr, -1
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%and = and i64 %not, 1
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ret i64 %and
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}
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define i64 @bittest_10_i64(i64 %a) nounwind {
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; RV64I-LABEL: bittest_10_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 1024
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; RV64I-NEXT: seqz a0, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_10_i64:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: andi a0, a0, 1024
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; RV64ZBS-NEXT: seqz a0, a0
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; RV64ZBS-NEXT: ret
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%shr = lshr i64 %a, 10
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%not = xor i64 %shr, -1
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%and = and i64 %not, 1
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ret i64 %and
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}
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define i64 @bittest_11_i64(i64 %a) nounwind {
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; RV64I-LABEL: bittest_11_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srli a0, a0, 11
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; RV64I-NEXT: not a0, a0
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_11_i64:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: bexti a0, a0, 11
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; RV64ZBS-NEXT: xori a0, a0, 1
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; RV64ZBS-NEXT: ret
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%shr = lshr i64 %a, 11
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%not = xor i64 %shr, -1
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%and = and i64 %not, 1
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ret i64 %and
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}
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define i64 @bittest_31_i64(i64 %a) nounwind {
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; RV64I-LABEL: bittest_31_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srli a0, a0, 31
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; RV64I-NEXT: not a0, a0
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_31_i64:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: bexti a0, a0, 31
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; RV64ZBS-NEXT: xori a0, a0, 1
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; RV64ZBS-NEXT: ret
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%shr = lshr i64 %a, 31
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%not = xor i64 %shr, -1
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%and = and i64 %not, 1
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ret i64 %and
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}
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define i64 @bittest_32_i64(i64 %a) nounwind {
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; RV64I-LABEL: bittest_32_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: not a0, a0
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_32_i64:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: bexti a0, a0, 32
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; RV64ZBS-NEXT: xori a0, a0, 1
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; RV64ZBS-NEXT: ret
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%shr = lshr i64 %a, 32
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%not = xor i64 %shr, -1
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%and = and i64 %not, 1
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ret i64 %and
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}
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define i64 @bittest_63_i64(i64 %a) nounwind {
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; RV64I-LABEL: bittest_63_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: not a0, a0
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; RV64I-NEXT: srli a0, a0, 63
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; RV64I-NEXT: ret
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;
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; RV64ZBS-LABEL: bittest_63_i64:
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; RV64ZBS: # %bb.0:
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; RV64ZBS-NEXT: not a0, a0
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; RV64ZBS-NEXT: srli a0, a0, 63
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; RV64ZBS-NEXT: ret
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%shr = lshr i64 %a, 63
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%not = xor i64 %shr, -1
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%and = and i64 %not, 1
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ret i64 %and
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}
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