llvm-project/llvm/test/CodeGen/RISCV/copy-frameindex.mir
Hsiangkai Wang facff468b6 [RISCV] Reorder the vector register allocation order.
GPR uses argument registers as the first group of registers to allocate.
This patch uses vector argument registers, v8 to v23, as the first group
to allocate.

Differential Revision: https://reviews.llvm.org/D111304
2021-10-19 09:30:13 +08:00

66 lines
2.2 KiB
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=riscv64 -debugify-and-strip-all-safe -run-pass machine-sink %s -o - 2>&1 | FileCheck %s
--- |
define void @sink_addi_fi(i32 %0) !dbg !5 {
bb.0:
%1 = alloca i32, align 4
call void @llvm.dbg.value(metadata i32* %1, metadata !1, metadata !DIExpression()), !dbg !3
%2 = icmp eq i32 %0, 0
br i1 %2, label %bb.2, label %bb.1
bb.1:
store volatile i32 0, i32* %1, align 4
br label %bb.2
bb.2:
ret void
}
declare void @llvm.dbg.value(metadata, metadata, metadata)
!llvm.dbg.cu = !{!0}
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !4)
!1 = !DILocalVariable(name: "var", scope: !5, file: !4, line: 2, type: !2)
!2 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned)
!3 = !DILocation(line: 0, scope: !5)
!4 = !DIFile(filename: "test.c", directory: "")
!5 = distinct !DISubprogram(name: "sink_addi_fi", scope: !4, file: !4, line: 1, type: !6, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !8)
!6 = !DISubroutineType(types: !7)
!7 = !{null, !2}
!8 = !{}
...
---
name: sink_addi_fi
liveins:
- { reg: '$x10', virtual-reg: '%0' }
stack:
- { id: 0, offset: 0, size: 4, alignment: 4 }
body: |
; CHECK-LABEL: name: sink_addi_fi
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: BEQ killed [[COPY]], $x0, %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0, 0
; CHECK-NEXT: SW $x0, killed [[ADDI]], 0 :: (volatile store (s32) into %stack.0)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: PseudoRET
bb.0:
liveins: $x10
%0:gpr = COPY $x10
DBG_VALUE %stack.0, $noreg, !1, !DIExpression(), debug-location !3
%1:gpr = ADDI %stack.0, 0
DBG_VALUE %1, $noreg, !1, !DIExpression(DW_OP_plus_uconst, 0, DW_OP_stack_value), debug-location !3
BEQ killed %0:gpr, $x0, %bb.2
bb.1:
SW $x0, killed %1:gpr, 0 :: (volatile store (s32) into %stack.0, align 4)
bb.2:
PseudoRET