bd653f6406
Now AND is used for zero extension when both Zbb and Zbp are not enabled. It may be better to use shift operation if the trailing ones mask exceeds simm12. This patch optimzes LUI+ADDI+AND to SLLI+SRLI. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D116720
123 lines
3.5 KiB
LLVM
123 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IF %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IF %s
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; This file tests cases where simple floating point operations can be
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; profitably handled though bit manipulation if a soft-float ABI is being used
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; (e.g. fneg implemented by XORing the sign bit). This is typically handled in
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; DAGCombiner::visitBITCAST, but this target-independent code may not trigger
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; in cases where we perform custom legalisation (e.g. RV64F).
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define float @fneg(float %a) nounwind {
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; RV32I-LABEL: fneg:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 524288
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32IF-LABEL: fneg:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: lui a1, 524288
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; RV32IF-NEXT: xor a0, a0, a1
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; RV32IF-NEXT: ret
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;
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; RV64I-LABEL: fneg:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 524288
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64IF-LABEL: fneg:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: lui a1, 524288
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; RV64IF-NEXT: xor a0, a0, a1
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; RV64IF-NEXT: ret
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%1 = fneg float %a
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ret float %1
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}
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declare float @llvm.fabs.f32(float)
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define float @fabs(float %a) nounwind {
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; RV32I-LABEL: fabs:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 1
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; RV32I-NEXT: srli a0, a0, 1
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; RV32I-NEXT: ret
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;
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; RV32IF-LABEL: fabs:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: slli a0, a0, 1
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; RV32IF-NEXT: srli a0, a0, 1
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; RV32IF-NEXT: ret
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;
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; RV64I-LABEL: fabs:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 33
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; RV64I-NEXT: srli a0, a0, 33
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; RV64I-NEXT: ret
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;
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; RV64IF-LABEL: fabs:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: slli a0, a0, 33
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; RV64IF-NEXT: srli a0, a0, 33
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; RV64IF-NEXT: ret
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%1 = call float @llvm.fabs.f32(float %a)
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ret float %1
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}
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declare float @llvm.copysign.f32(float, float)
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; DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN will convert to bitwise
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; operations if floating point isn't supported. A combine could be written to
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; do the same even when f32 is legal.
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define float @fcopysign_fneg(float %a, float %b) nounwind {
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; RV32I-LABEL: fcopysign_fneg:
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; RV32I: # %bb.0:
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; RV32I-NEXT: not a1, a1
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; RV32I-NEXT: lui a2, 524288
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; RV32I-NEXT: and a1, a1, a2
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; RV32I-NEXT: slli a0, a0, 1
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; RV32I-NEXT: srli a0, a0, 1
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32IF-LABEL: fcopysign_fneg:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: lui a2, 524288
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; RV32IF-NEXT: xor a1, a1, a2
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fsgnj.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64I-LABEL: fcopysign_fneg:
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; RV64I: # %bb.0:
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; RV64I-NEXT: not a1, a1
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; RV64I-NEXT: lui a2, 524288
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; RV64I-NEXT: and a1, a1, a2
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; RV64I-NEXT: slli a0, a0, 33
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; RV64I-NEXT: srli a0, a0, 33
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64IF-LABEL: fcopysign_fneg:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fsgnjn.s ft0, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = fneg float %b
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%2 = call float @llvm.copysign.f32(float %a, float %1)
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ret float %2
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}
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