659363c0cc
Since we mark the pseudos as mayLoad but do not provide any MMOs, isSafeToMove conservatively returns false, stopping MachineLICM from hoisting the instructions. PseudoLA_TLS_GD does not actually expand to a load, so stop marking that as mayLoad to allow it to be hoisted, and for the others make sure to add MMOs during lowering to indicate they're GOT loads and thus can be freely moved. Fixes https://github.com/llvm/llvm-project/issues/54372 Reviewed By: MaskRay, arichardson Differential Revision: https://reviews.llvm.org/D121654
75 lines
2.9 KiB
LLVM
75 lines
2.9 KiB
LLVM
; RUN: llc -mtriple=riscv32 --code-model=small \
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; RUN: -stop-after riscv-expand-pseudo %s -o %t.mir
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; RUN: llc -mtriple=riscv32 -run-pass none %t.mir -o - | \
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; RUN: FileCheck %s -check-prefix=RV32-SMALL
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;
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; RUN: llc -mtriple=riscv32 --code-model=medium --relocation-model=pic \
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; RUN: -stop-after riscv-expand-pseudo %s -o %t.mir
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; RUN: llc -mtriple=riscv32 -run-pass none %t.mir -o - | \
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; RUN: FileCheck %s -check-prefix=RV32-MED
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; This tests the RISC-V-specific serialization and deserialization of
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; `target-flags(...)`
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@g_e = external global i32
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@g_i = internal global i32 0
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@t_un = external thread_local global i32
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@t_ld = external thread_local(localdynamic) global i32
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@t_ie = external thread_local(initialexec) global i32
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@t_le = external thread_local(localexec) global i32
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declare i32 @callee(i32) nounwind
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define i32 @caller(i32 %a) nounwind {
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; RV32-SMALL-LABEL: name: caller
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; RV32-SMALL: target-flags(riscv-hi) @g_e
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; RV32-SMALL-NEXT: target-flags(riscv-lo) @g_e
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; RV32-SMALL: target-flags(riscv-tls-got-hi) @t_un
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; RV32-SMALL-NEXT: target-flags(riscv-pcrel-lo) %bb.1
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; RV32-SMALL: target-flags(riscv-hi) @g_i
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; RV32-SMALL-NEXT: target-flags(riscv-lo) @g_i
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; RV32-SMALL: target-flags(riscv-tls-got-hi) @t_ld
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; RV32-SMALL-NEXT: target-flags(riscv-pcrel-lo) %bb.2
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; RV32-SMALL: target-flags(riscv-tls-got-hi) @t_ie
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; RV32-SMALL-NEXT: target-flags(riscv-pcrel-lo) %bb.3
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; RV32-SMALL: target-flags(riscv-tprel-hi) @t_le
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; RV32-SMALL-NEXT: target-flags(riscv-tprel-add) @t_le
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; RV32-SMALL-NEXT: target-flags(riscv-tprel-lo) @t_le
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; RV32-SMALL: target-flags(riscv-plt) @callee
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;
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; RV32-MED-LABEL: name: caller
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; RV32-MED: target-flags(riscv-got-hi) @g_e
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; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.1
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; RV32-MED: target-flags(riscv-pcrel-hi) @g_i
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; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.2
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; RV32-MED: target-flags(riscv-tls-gd-hi) @t_un
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; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.3
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; RV32-MED-NEXT: target-flags(riscv-plt) &__tls_get_addr
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; RV32-MED: target-flags(riscv-tls-gd-hi) @t_ld
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; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.4
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; RV32-MED-NEXT: target-flags(riscv-plt) &__tls_get_addr
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; RV32-MED: target-flags(riscv-tls-got-hi) @t_ie
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; RV32-MED-NEXT: target-flags(riscv-pcrel-lo) %bb.5
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; RV32-MED: target-flags(riscv-tprel-hi) @t_le
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; RV32-MED-NEXT: target-flags(riscv-tprel-add) @t_le
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; RV32-MED-NEXT: target-flags(riscv-tprel-lo) @t_le
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; RV32-MED: target-flags(riscv-plt) @callee
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;
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%b = load i32, i32* @g_e
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%c = load i32, i32* @g_i
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%d = load i32, i32* @t_un
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%e = load i32, i32* @t_ld
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%f = load i32, i32* @t_ie
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%g = load i32, i32* @t_le
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%sum = bitcast i32 0 to i32
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%sum.a = add i32 %sum, %a
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%sum.b = add i32 %sum.a, %b
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%sum.c = add i32 %sum.b, %c
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%sum.d = add i32 %sum.c, %d
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%sum.e = add i32 %sum.d, %e
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%sum.f = add i32 %sum.e, %f
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%sum.g = add i32 %sum.f, %g
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%retval = call i32 @callee(i32 %sum.g)
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ret i32 %retval
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}
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