553 lines
15 KiB
LLVM
553 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32ZBB
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; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64ZBB
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; These IR sequences are idioms for rotates. If rotate instructions are
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; supported, they will be turned into ISD::ROTL or ISD::ROTR.
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define i32 @rotl_32(i32 %x, i32 %y) nounwind {
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; RV32I-LABEL: rotl_32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: neg a2, a1
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; RV32I-NEXT: sll a1, a0, a1
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; RV32I-NEXT: srl a0, a0, a2
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; RV32I-NEXT: or a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: rotl_32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: negw a2, a1
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; RV64I-NEXT: sllw a1, a0, a1
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; RV64I-NEXT: srlw a0, a0, a2
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV32ZBB-LABEL: rotl_32:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: rol a0, a0, a1
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; RV32ZBB-NEXT: ret
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;
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; RV64ZBB-LABEL: rotl_32:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: rolw a0, a0, a1
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; RV64ZBB-NEXT: ret
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%z = sub i32 32, %y
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%b = shl i32 %x, %y
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%c = lshr i32 %x, %z
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%d = or i32 %b, %c
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ret i32 %d
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}
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define i32 @rotr_32(i32 %x, i32 %y) nounwind {
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; RV32I-LABEL: rotr_32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: neg a2, a1
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; RV32I-NEXT: srl a1, a0, a1
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; RV32I-NEXT: sll a0, a0, a2
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; RV32I-NEXT: or a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: rotr_32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: negw a2, a1
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; RV64I-NEXT: srlw a1, a0, a1
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; RV64I-NEXT: sllw a0, a0, a2
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV32ZBB-LABEL: rotr_32:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: ror a0, a0, a1
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; RV32ZBB-NEXT: ret
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;
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; RV64ZBB-LABEL: rotr_32:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: rorw a0, a0, a1
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; RV64ZBB-NEXT: ret
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%z = sub i32 32, %y
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%b = lshr i32 %x, %y
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%c = shl i32 %x, %z
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%d = or i32 %b, %c
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ret i32 %d
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}
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define i64 @rotl_64(i64 %x, i64 %y) nounwind {
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; RV32I-LABEL: rotl_64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a5, a2, -32
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; RV32I-NEXT: mv a4, a1
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; RV32I-NEXT: bltz a5, .LBB2_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sll a1, a0, a5
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; RV32I-NEXT: j .LBB2_3
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; RV32I-NEXT: .LBB2_2:
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; RV32I-NEXT: sll a1, a4, a2
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; RV32I-NEXT: xori a3, a2, 31
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; RV32I-NEXT: srli a6, a0, 1
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; RV32I-NEXT: srl a3, a6, a3
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; RV32I-NEXT: or a1, a1, a3
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; RV32I-NEXT: .LBB2_3:
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; RV32I-NEXT: neg a6, a2
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; RV32I-NEXT: li a3, 32
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; RV32I-NEXT: sub a7, a3, a2
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; RV32I-NEXT: srl a3, a4, a6
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; RV32I-NEXT: bltz a7, .LBB2_6
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; RV32I-NEXT: # %bb.4:
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; RV32I-NEXT: bltz a5, .LBB2_7
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; RV32I-NEXT: .LBB2_5:
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; RV32I-NEXT: mv a0, a3
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB2_6:
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; RV32I-NEXT: srl a6, a0, a6
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; RV32I-NEXT: li a7, 64
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; RV32I-NEXT: sub a7, a7, a2
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; RV32I-NEXT: xori a7, a7, 31
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; RV32I-NEXT: slli a4, a4, 1
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; RV32I-NEXT: sll a4, a4, a7
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; RV32I-NEXT: or a4, a6, a4
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; RV32I-NEXT: or a1, a1, a3
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; RV32I-NEXT: mv a3, a4
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; RV32I-NEXT: bgez a5, .LBB2_5
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; RV32I-NEXT: .LBB2_7:
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; RV32I-NEXT: sll a0, a0, a2
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; RV32I-NEXT: or a3, a3, a0
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; RV32I-NEXT: mv a0, a3
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: rotl_64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: negw a2, a1
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; RV64I-NEXT: sll a1, a0, a1
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; RV64I-NEXT: srl a0, a0, a2
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV32ZBB-LABEL: rotl_64:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: addi a5, a2, -32
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; RV32ZBB-NEXT: mv a4, a1
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; RV32ZBB-NEXT: bltz a5, .LBB2_2
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; RV32ZBB-NEXT: # %bb.1:
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; RV32ZBB-NEXT: sll a1, a0, a5
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; RV32ZBB-NEXT: j .LBB2_3
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; RV32ZBB-NEXT: .LBB2_2:
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; RV32ZBB-NEXT: sll a1, a4, a2
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; RV32ZBB-NEXT: xori a3, a2, 31
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; RV32ZBB-NEXT: srli a6, a0, 1
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; RV32ZBB-NEXT: srl a3, a6, a3
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; RV32ZBB-NEXT: or a1, a1, a3
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; RV32ZBB-NEXT: .LBB2_3:
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; RV32ZBB-NEXT: neg a6, a2
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; RV32ZBB-NEXT: li a3, 32
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; RV32ZBB-NEXT: sub a7, a3, a2
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; RV32ZBB-NEXT: srl a3, a4, a6
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; RV32ZBB-NEXT: bltz a7, .LBB2_6
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; RV32ZBB-NEXT: # %bb.4:
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; RV32ZBB-NEXT: bltz a5, .LBB2_7
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; RV32ZBB-NEXT: .LBB2_5:
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; RV32ZBB-NEXT: mv a0, a3
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; RV32ZBB-NEXT: ret
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; RV32ZBB-NEXT: .LBB2_6:
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; RV32ZBB-NEXT: srl a6, a0, a6
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; RV32ZBB-NEXT: li a7, 64
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; RV32ZBB-NEXT: sub a7, a7, a2
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; RV32ZBB-NEXT: xori a7, a7, 31
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; RV32ZBB-NEXT: slli a4, a4, 1
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; RV32ZBB-NEXT: sll a4, a4, a7
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; RV32ZBB-NEXT: or a4, a6, a4
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; RV32ZBB-NEXT: or a1, a1, a3
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; RV32ZBB-NEXT: mv a3, a4
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; RV32ZBB-NEXT: bgez a5, .LBB2_5
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; RV32ZBB-NEXT: .LBB2_7:
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; RV32ZBB-NEXT: sll a0, a0, a2
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; RV32ZBB-NEXT: or a3, a3, a0
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; RV32ZBB-NEXT: mv a0, a3
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; RV32ZBB-NEXT: ret
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;
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; RV64ZBB-LABEL: rotl_64:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: rol a0, a0, a1
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; RV64ZBB-NEXT: ret
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%z = sub i64 64, %y
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%b = shl i64 %x, %y
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%c = lshr i64 %x, %z
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%d = or i64 %b, %c
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ret i64 %d
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}
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define i64 @rotr_64(i64 %x, i64 %y) nounwind {
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; RV32I-LABEL: rotr_64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a5, a2, -32
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; RV32I-NEXT: mv a4, a0
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; RV32I-NEXT: bltz a5, .LBB3_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: srl a0, a1, a5
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; RV32I-NEXT: j .LBB3_3
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; RV32I-NEXT: .LBB3_2:
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; RV32I-NEXT: srl a0, a4, a2
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; RV32I-NEXT: xori a3, a2, 31
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; RV32I-NEXT: slli a6, a1, 1
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; RV32I-NEXT: sll a3, a6, a3
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; RV32I-NEXT: or a0, a0, a3
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; RV32I-NEXT: .LBB3_3:
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; RV32I-NEXT: neg a6, a2
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; RV32I-NEXT: li a3, 32
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; RV32I-NEXT: sub a7, a3, a2
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; RV32I-NEXT: sll a3, a4, a6
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; RV32I-NEXT: bltz a7, .LBB3_6
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; RV32I-NEXT: # %bb.4:
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; RV32I-NEXT: bltz a5, .LBB3_7
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; RV32I-NEXT: .LBB3_5:
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; RV32I-NEXT: mv a1, a3
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB3_6:
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; RV32I-NEXT: sll a6, a1, a6
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; RV32I-NEXT: li a7, 64
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; RV32I-NEXT: sub a7, a7, a2
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; RV32I-NEXT: xori a7, a7, 31
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; RV32I-NEXT: srli a4, a4, 1
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; RV32I-NEXT: srl a4, a4, a7
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; RV32I-NEXT: or a4, a6, a4
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; RV32I-NEXT: or a0, a0, a3
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; RV32I-NEXT: mv a3, a4
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; RV32I-NEXT: bgez a5, .LBB3_5
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; RV32I-NEXT: .LBB3_7:
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; RV32I-NEXT: srl a1, a1, a2
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; RV32I-NEXT: or a3, a3, a1
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; RV32I-NEXT: mv a1, a3
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: rotr_64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: negw a2, a1
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; RV64I-NEXT: srl a1, a0, a1
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; RV64I-NEXT: sll a0, a0, a2
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV32ZBB-LABEL: rotr_64:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: addi a5, a2, -32
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; RV32ZBB-NEXT: mv a4, a0
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; RV32ZBB-NEXT: bltz a5, .LBB3_2
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; RV32ZBB-NEXT: # %bb.1:
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; RV32ZBB-NEXT: srl a0, a1, a5
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; RV32ZBB-NEXT: j .LBB3_3
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; RV32ZBB-NEXT: .LBB3_2:
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; RV32ZBB-NEXT: srl a0, a4, a2
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; RV32ZBB-NEXT: xori a3, a2, 31
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; RV32ZBB-NEXT: slli a6, a1, 1
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; RV32ZBB-NEXT: sll a3, a6, a3
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; RV32ZBB-NEXT: or a0, a0, a3
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; RV32ZBB-NEXT: .LBB3_3:
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; RV32ZBB-NEXT: neg a6, a2
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; RV32ZBB-NEXT: li a3, 32
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; RV32ZBB-NEXT: sub a7, a3, a2
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; RV32ZBB-NEXT: sll a3, a4, a6
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; RV32ZBB-NEXT: bltz a7, .LBB3_6
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; RV32ZBB-NEXT: # %bb.4:
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; RV32ZBB-NEXT: bltz a5, .LBB3_7
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; RV32ZBB-NEXT: .LBB3_5:
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; RV32ZBB-NEXT: mv a1, a3
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; RV32ZBB-NEXT: ret
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; RV32ZBB-NEXT: .LBB3_6:
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; RV32ZBB-NEXT: sll a6, a1, a6
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; RV32ZBB-NEXT: li a7, 64
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; RV32ZBB-NEXT: sub a7, a7, a2
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; RV32ZBB-NEXT: xori a7, a7, 31
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; RV32ZBB-NEXT: srli a4, a4, 1
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; RV32ZBB-NEXT: srl a4, a4, a7
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; RV32ZBB-NEXT: or a4, a6, a4
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; RV32ZBB-NEXT: or a0, a0, a3
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; RV32ZBB-NEXT: mv a3, a4
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; RV32ZBB-NEXT: bgez a5, .LBB3_5
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; RV32ZBB-NEXT: .LBB3_7:
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; RV32ZBB-NEXT: srl a1, a1, a2
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; RV32ZBB-NEXT: or a3, a3, a1
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; RV32ZBB-NEXT: mv a1, a3
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; RV32ZBB-NEXT: ret
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;
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; RV64ZBB-LABEL: rotr_64:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: ror a0, a0, a1
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; RV64ZBB-NEXT: ret
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%z = sub i64 64, %y
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%b = lshr i64 %x, %y
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%c = shl i64 %x, %z
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%d = or i64 %b, %c
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ret i64 %d
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}
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define i32 @rotl_32_mask(i32 %x, i32 %y) nounwind {
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; RV32I-LABEL: rotl_32_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: neg a2, a1
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; RV32I-NEXT: sll a1, a0, a1
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; RV32I-NEXT: srl a0, a0, a2
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; RV32I-NEXT: or a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: rotl_32_mask:
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; RV64I: # %bb.0:
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; RV64I-NEXT: negw a2, a1
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; RV64I-NEXT: sllw a1, a0, a1
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; RV64I-NEXT: srlw a0, a0, a2
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV32ZBB-LABEL: rotl_32_mask:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: rol a0, a0, a1
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; RV32ZBB-NEXT: ret
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;
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; RV64ZBB-LABEL: rotl_32_mask:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: rolw a0, a0, a1
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; RV64ZBB-NEXT: ret
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%z = sub i32 0, %y
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%and = and i32 %z, 31
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%b = shl i32 %x, %y
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%c = lshr i32 %x, %and
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%d = or i32 %b, %c
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ret i32 %d
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}
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define i32 @rotr_32_mask(i32 %x, i32 %y) nounwind {
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; RV32I-LABEL: rotr_32_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: neg a2, a1
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; RV32I-NEXT: srl a1, a0, a1
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; RV32I-NEXT: sll a0, a0, a2
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; RV32I-NEXT: or a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: rotr_32_mask:
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; RV64I: # %bb.0:
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; RV64I-NEXT: negw a2, a1
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; RV64I-NEXT: srlw a1, a0, a1
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; RV64I-NEXT: sllw a0, a0, a2
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV32ZBB-LABEL: rotr_32_mask:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: ror a0, a0, a1
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; RV32ZBB-NEXT: ret
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;
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; RV64ZBB-LABEL: rotr_32_mask:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: rorw a0, a0, a1
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; RV64ZBB-NEXT: ret
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%z = sub i32 0, %y
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%and = and i32 %z, 31
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%b = lshr i32 %x, %y
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%c = shl i32 %x, %and
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%d = or i32 %b, %c
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ret i32 %d
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}
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define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {
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; RV32I-LABEL: rotl_64_mask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a5, a2, -32
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; RV32I-NEXT: mv a3, a1
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; RV32I-NEXT: bltz a5, .LBB6_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sll a1, a0, a5
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; RV32I-NEXT: j .LBB6_3
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; RV32I-NEXT: .LBB6_2:
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; RV32I-NEXT: sll a1, a3, a2
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; RV32I-NEXT: xori a4, a2, 31
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; RV32I-NEXT: srli a6, a0, 1
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; RV32I-NEXT: srl a4, a6, a4
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; RV32I-NEXT: or a1, a1, a4
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; RV32I-NEXT: .LBB6_3:
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; RV32I-NEXT: neg a6, a2
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; RV32I-NEXT: andi a4, a6, 63
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; RV32I-NEXT: addi a7, a4, -32
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; RV32I-NEXT: bltz a7, .LBB6_5
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; RV32I-NEXT: # %bb.4:
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; RV32I-NEXT: srl a4, a3, a7
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; RV32I-NEXT: bltz a5, .LBB6_6
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; RV32I-NEXT: j .LBB6_7
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; RV32I-NEXT: .LBB6_5:
|
|
; RV32I-NEXT: srl a7, a0, a6
|
|
; RV32I-NEXT: xori a4, a4, 31
|
|
; RV32I-NEXT: slli t0, a3, 1
|
|
; RV32I-NEXT: sll a4, t0, a4
|
|
; RV32I-NEXT: or a4, a7, a4
|
|
; RV32I-NEXT: srl a3, a3, a6
|
|
; RV32I-NEXT: or a1, a1, a3
|
|
; RV32I-NEXT: bgez a5, .LBB6_7
|
|
; RV32I-NEXT: .LBB6_6:
|
|
; RV32I-NEXT: sll a0, a0, a2
|
|
; RV32I-NEXT: or a4, a4, a0
|
|
; RV32I-NEXT: .LBB6_7:
|
|
; RV32I-NEXT: mv a0, a4
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: rotl_64_mask:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: neg a2, a1
|
|
; RV64I-NEXT: sll a1, a0, a1
|
|
; RV64I-NEXT: srl a0, a0, a2
|
|
; RV64I-NEXT: or a0, a1, a0
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV32ZBB-LABEL: rotl_64_mask:
|
|
; RV32ZBB: # %bb.0:
|
|
; RV32ZBB-NEXT: addi a5, a2, -32
|
|
; RV32ZBB-NEXT: mv a3, a1
|
|
; RV32ZBB-NEXT: bltz a5, .LBB6_2
|
|
; RV32ZBB-NEXT: # %bb.1:
|
|
; RV32ZBB-NEXT: sll a1, a0, a5
|
|
; RV32ZBB-NEXT: j .LBB6_3
|
|
; RV32ZBB-NEXT: .LBB6_2:
|
|
; RV32ZBB-NEXT: sll a1, a3, a2
|
|
; RV32ZBB-NEXT: xori a4, a2, 31
|
|
; RV32ZBB-NEXT: srli a6, a0, 1
|
|
; RV32ZBB-NEXT: srl a4, a6, a4
|
|
; RV32ZBB-NEXT: or a1, a1, a4
|
|
; RV32ZBB-NEXT: .LBB6_3:
|
|
; RV32ZBB-NEXT: neg a6, a2
|
|
; RV32ZBB-NEXT: andi a4, a6, 63
|
|
; RV32ZBB-NEXT: addi a7, a4, -32
|
|
; RV32ZBB-NEXT: bltz a7, .LBB6_5
|
|
; RV32ZBB-NEXT: # %bb.4:
|
|
; RV32ZBB-NEXT: srl a4, a3, a7
|
|
; RV32ZBB-NEXT: bltz a5, .LBB6_6
|
|
; RV32ZBB-NEXT: j .LBB6_7
|
|
; RV32ZBB-NEXT: .LBB6_5:
|
|
; RV32ZBB-NEXT: srl a7, a0, a6
|
|
; RV32ZBB-NEXT: xori a4, a4, 31
|
|
; RV32ZBB-NEXT: slli t0, a3, 1
|
|
; RV32ZBB-NEXT: sll a4, t0, a4
|
|
; RV32ZBB-NEXT: or a4, a7, a4
|
|
; RV32ZBB-NEXT: srl a3, a3, a6
|
|
; RV32ZBB-NEXT: or a1, a1, a3
|
|
; RV32ZBB-NEXT: bgez a5, .LBB6_7
|
|
; RV32ZBB-NEXT: .LBB6_6:
|
|
; RV32ZBB-NEXT: sll a0, a0, a2
|
|
; RV32ZBB-NEXT: or a4, a4, a0
|
|
; RV32ZBB-NEXT: .LBB6_7:
|
|
; RV32ZBB-NEXT: mv a0, a4
|
|
; RV32ZBB-NEXT: ret
|
|
;
|
|
; RV64ZBB-LABEL: rotl_64_mask:
|
|
; RV64ZBB: # %bb.0:
|
|
; RV64ZBB-NEXT: rol a0, a0, a1
|
|
; RV64ZBB-NEXT: ret
|
|
%z = sub i64 0, %y
|
|
%and = and i64 %z, 63
|
|
%b = shl i64 %x, %y
|
|
%c = lshr i64 %x, %and
|
|
%d = or i64 %b, %c
|
|
ret i64 %d
|
|
}
|
|
|
|
define i64 @rotr_64_mask(i64 %x, i64 %y) nounwind {
|
|
; RV32I-LABEL: rotr_64_mask:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: addi a5, a2, -32
|
|
; RV32I-NEXT: mv a3, a0
|
|
; RV32I-NEXT: bltz a5, .LBB7_2
|
|
; RV32I-NEXT: # %bb.1:
|
|
; RV32I-NEXT: srl a0, a1, a5
|
|
; RV32I-NEXT: j .LBB7_3
|
|
; RV32I-NEXT: .LBB7_2:
|
|
; RV32I-NEXT: srl a0, a3, a2
|
|
; RV32I-NEXT: xori a4, a2, 31
|
|
; RV32I-NEXT: slli a6, a1, 1
|
|
; RV32I-NEXT: sll a4, a6, a4
|
|
; RV32I-NEXT: or a0, a0, a4
|
|
; RV32I-NEXT: .LBB7_3:
|
|
; RV32I-NEXT: neg a6, a2
|
|
; RV32I-NEXT: andi a4, a6, 63
|
|
; RV32I-NEXT: addi a7, a4, -32
|
|
; RV32I-NEXT: bltz a7, .LBB7_5
|
|
; RV32I-NEXT: # %bb.4:
|
|
; RV32I-NEXT: sll a4, a3, a7
|
|
; RV32I-NEXT: bltz a5, .LBB7_6
|
|
; RV32I-NEXT: j .LBB7_7
|
|
; RV32I-NEXT: .LBB7_5:
|
|
; RV32I-NEXT: sll a7, a1, a6
|
|
; RV32I-NEXT: xori a4, a4, 31
|
|
; RV32I-NEXT: srli t0, a3, 1
|
|
; RV32I-NEXT: srl a4, t0, a4
|
|
; RV32I-NEXT: or a4, a7, a4
|
|
; RV32I-NEXT: sll a3, a3, a6
|
|
; RV32I-NEXT: or a0, a0, a3
|
|
; RV32I-NEXT: bgez a5, .LBB7_7
|
|
; RV32I-NEXT: .LBB7_6:
|
|
; RV32I-NEXT: srl a1, a1, a2
|
|
; RV32I-NEXT: or a4, a4, a1
|
|
; RV32I-NEXT: .LBB7_7:
|
|
; RV32I-NEXT: mv a1, a4
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV64I-LABEL: rotr_64_mask:
|
|
; RV64I: # %bb.0:
|
|
; RV64I-NEXT: neg a2, a1
|
|
; RV64I-NEXT: srl a1, a0, a1
|
|
; RV64I-NEXT: sll a0, a0, a2
|
|
; RV64I-NEXT: or a0, a1, a0
|
|
; RV64I-NEXT: ret
|
|
;
|
|
; RV32ZBB-LABEL: rotr_64_mask:
|
|
; RV32ZBB: # %bb.0:
|
|
; RV32ZBB-NEXT: addi a5, a2, -32
|
|
; RV32ZBB-NEXT: mv a3, a0
|
|
; RV32ZBB-NEXT: bltz a5, .LBB7_2
|
|
; RV32ZBB-NEXT: # %bb.1:
|
|
; RV32ZBB-NEXT: srl a0, a1, a5
|
|
; RV32ZBB-NEXT: j .LBB7_3
|
|
; RV32ZBB-NEXT: .LBB7_2:
|
|
; RV32ZBB-NEXT: srl a0, a3, a2
|
|
; RV32ZBB-NEXT: xori a4, a2, 31
|
|
; RV32ZBB-NEXT: slli a6, a1, 1
|
|
; RV32ZBB-NEXT: sll a4, a6, a4
|
|
; RV32ZBB-NEXT: or a0, a0, a4
|
|
; RV32ZBB-NEXT: .LBB7_3:
|
|
; RV32ZBB-NEXT: neg a6, a2
|
|
; RV32ZBB-NEXT: andi a4, a6, 63
|
|
; RV32ZBB-NEXT: addi a7, a4, -32
|
|
; RV32ZBB-NEXT: bltz a7, .LBB7_5
|
|
; RV32ZBB-NEXT: # %bb.4:
|
|
; RV32ZBB-NEXT: sll a4, a3, a7
|
|
; RV32ZBB-NEXT: bltz a5, .LBB7_6
|
|
; RV32ZBB-NEXT: j .LBB7_7
|
|
; RV32ZBB-NEXT: .LBB7_5:
|
|
; RV32ZBB-NEXT: sll a7, a1, a6
|
|
; RV32ZBB-NEXT: xori a4, a4, 31
|
|
; RV32ZBB-NEXT: srli t0, a3, 1
|
|
; RV32ZBB-NEXT: srl a4, t0, a4
|
|
; RV32ZBB-NEXT: or a4, a7, a4
|
|
; RV32ZBB-NEXT: sll a3, a3, a6
|
|
; RV32ZBB-NEXT: or a0, a0, a3
|
|
; RV32ZBB-NEXT: bgez a5, .LBB7_7
|
|
; RV32ZBB-NEXT: .LBB7_6:
|
|
; RV32ZBB-NEXT: srl a1, a1, a2
|
|
; RV32ZBB-NEXT: or a4, a4, a1
|
|
; RV32ZBB-NEXT: .LBB7_7:
|
|
; RV32ZBB-NEXT: mv a1, a4
|
|
; RV32ZBB-NEXT: ret
|
|
;
|
|
; RV64ZBB-LABEL: rotr_64_mask:
|
|
; RV64ZBB: # %bb.0:
|
|
; RV64ZBB-NEXT: ror a0, a0, a1
|
|
; RV64ZBB-NEXT: ret
|
|
%z = sub i64 0, %y
|
|
%and = and i64 %z, 63
|
|
%b = lshr i64 %x, %y
|
|
%c = shl i64 %x, %and
|
|
%d = or i64 %b, %c
|
|
ret i64 %d
|
|
}
|