402f2cae7d
Given a sextload i16, we can usually generate "ldrsh [rn. rm]". If we don't naturally have a rn, rm addressing mode, we can either generate "ldrh [rn, #0]; sxth" or "mov rm, #0; ldrsh [rn. rm]". We currently generate the first, always creating a sxth. They are both the same number of instructions, but if we generate the second then the mov #0 will likely be CSE'd or pulled out of a loop, etc. This adjusts the ISel patterns to do that, creating a mov instead of a sxth. Differential Revision: https://reviews.llvm.org/D98693
58 lines
1.0 KiB
LLVM
58 lines
1.0 KiB
LLVM
; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=V5
|
|
; RUN: llc -mtriple=thumb-eabi -mattr=+v6 %s -o - | FileCheck %s -check-prefix=V6
|
|
|
|
; rdar://7176514
|
|
|
|
define i32 @test1(i8* %t1) nounwind {
|
|
; V5: ldrb
|
|
|
|
; V6: ldrb
|
|
%tmp.u = load i8, i8* %t1
|
|
%tmp1.s = zext i8 %tmp.u to i32
|
|
ret i32 %tmp1.s
|
|
}
|
|
|
|
define i32 @test2(i16* %t1) nounwind {
|
|
; V5: ldrh
|
|
|
|
; V6: ldrh
|
|
%tmp.u = load i16, i16* %t1
|
|
%tmp1.s = zext i16 %tmp.u to i32
|
|
ret i32 %tmp1.s
|
|
}
|
|
|
|
define i32 @test3(i8* %t0) nounwind {
|
|
; V5: ldrb
|
|
; V5: lsls
|
|
; V5: asrs
|
|
|
|
; V6: mov
|
|
; V6: ldrsb
|
|
%tmp.s = load i8, i8* %t0
|
|
%tmp1.s = sext i8 %tmp.s to i32
|
|
ret i32 %tmp1.s
|
|
}
|
|
|
|
define i32 @test4(i16* %t0) nounwind {
|
|
; V5: ldrh
|
|
; V5: lsls
|
|
; V5: asrs
|
|
|
|
; V6: mov
|
|
; V6: ldrsh
|
|
%tmp.s = load i16, i16* %t0
|
|
%tmp1.s = sext i16 %tmp.s to i32
|
|
ret i32 %tmp1.s
|
|
}
|
|
|
|
define i32 @test5() nounwind {
|
|
; V5: movs r0, #0
|
|
; V5: ldrsh
|
|
|
|
; V6: movs r0, #0
|
|
; V6: ldrsh
|
|
%tmp.s = load i16, i16* null
|
|
%tmp1.s = sext i16 %tmp.s to i32
|
|
ret i32 %tmp1.s
|
|
}
|