llvm-project/llvm/test/CodeGen/X86/block-placement.mir
Simon Pilgrim d391e4fe84 [X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC
Be more consistent in the naming convention for the various RET instructions to specify in terms of bitwidth.

Helps prevent future scheduler model mismatches like those that were only addressed in D44687.

Differential Revision: https://reviews.llvm.org/D113302
2021-11-07 15:06:54 +00:00

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# RUN: llc -mtriple=x86_64-apple-macosx10.12.0 -O3 -run-pass=block-placement -o - %s | FileCheck %s
--- |
; ModuleID = 'test.ll'
source_filename = "test.ll"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
declare void @stub(i32*)
define i32 @f(i32* %ptr, i1 %cond) {
entry:
br i1 %cond, label %left, label %right
left: ; preds = %entry
%is_null = icmp eq i32* %ptr, null
br i1 %is_null, label %null, label %not_null, !prof !0, !make.implicit !1
not_null: ; preds = %left
%val = load i32, i32* %ptr
ret i32 %val
null: ; preds = %left
call void @stub(i32* %ptr)
unreachable
right: ; preds = %entry
call void @stub(i32* null)
unreachable
}
; Function Attrs: nounwind
declare void @llvm.stackprotector(i8*, i8**) #0
attributes #0 = { nounwind }
!0 = !{!"branch_weights", i32 1048575, i32 1}
!1 = !{}
...
---
# CHECK: name: f
name: f
alignment: 16
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
- { reg: '$esi' }
# CHECK: $eax = FAULTING_OP 1, %bb.3, 1684, killed $rdi, 1, $noreg, 0, $noreg :: (load (s32) from %ir.ptr)
# CHECK-NEXT: JMP_1 %bb.2
# CHECK: bb.3.null:
# CHECK: bb.4.right:
# CHECK: bb.2.not_null:
body: |
bb.0.entry:
successors: %bb.1(0x7ffff800), %bb.3(0x00000800)
liveins: $esi, $rdi
frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
CFI_INSTRUCTION def_cfa_offset 16
TEST8ri $sil, 1, implicit-def $eflags, implicit killed $esi
JCC_1 %bb.3, 4, implicit killed $eflags
bb.1.left:
successors: %bb.2(0x7ffff800), %bb.4(0x00000800)
liveins: $rdi
$eax = FAULTING_OP 1, %bb.2, 1684, killed $rdi, 1, $noreg, 0, $noreg :: (load (s32) from %ir.ptr)
JMP_1 %bb.4
bb.4.not_null:
liveins: $rdi, $eax
$rcx = POP64r implicit-def $rsp, implicit $rsp
RET64 $eax
bb.2.null:
liveins: $rdi
CALL64pcrel32 @stub, csr_64, implicit $rsp, implicit $rdi, implicit-def $rsp
bb.3.right:
dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi
CALL64pcrel32 @stub, csr_64, implicit $rsp, implicit $rdi, implicit-def $rsp
...