acb96ffd14
LOGIC (LOGIC (SH X0, Y), Z), (SH X1, Y) --> LOGIC (SH (LOGIC X0, X1), Y), Z https://alive2.llvm.org/ce/z/QmR9rR This is a reassociation + factoring fold. The common shift operation is moved after a bitwise logic op on 2 input operands. We get simpler cases of these patterns in IR, but I suspect we would miss all of these exact tests in IR too. We also handle the simpler form of this plus several other folds in DAGCombiner::hoistLogicOpWithSameOpcodeHands(). This is a partial implementation of a transform suggested in D111530 (only handles 'or' bitwise logic as a first step - need to stamp out more tests for other opcodes). Several of the same tests added for D111530 are altered here (but not fully optimized). I'm not sure yet if this would help/hinder that patch, but this should be an improvement for all tests added with ecf606cb4329ae since it removes a shift operation in those examples. Differential Revision: https://reviews.llvm.org/D120516
309 lines
9.0 KiB
LLVM
309 lines
9.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=i686-- < %s | FileCheck %s --check-prefix=X86
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; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s --check-prefix=X64
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; Optimize expanded SRL/SHL used as an input of
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; SETCC comparing it with zero by removing rotation.
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;
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; See https://bugs.llvm.org/show_bug.cgi?id=50197
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define i128 @opt_setcc_lt_power_of_2(i128 %a) nounwind {
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; X86-LABEL: opt_setcc_lt_power_of_2:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebp
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; X86-NEXT: pushl %ebx
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X86-NEXT: .p2align 4, 0x90
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; X86-NEXT: .LBB0_1: # %loop
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; X86-NEXT: # =>This Inner Loop Header: Depth=1
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; X86-NEXT: addl $1, %edi
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; X86-NEXT: adcl $0, %esi
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; X86-NEXT: adcl $0, %edx
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; X86-NEXT: adcl $0, %ecx
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; X86-NEXT: movl %ecx, %ebx
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; X86-NEXT: shldl $4, %edx, %ebx
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; X86-NEXT: movl %esi, %ebp
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; X86-NEXT: orl %ecx, %ebp
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; X86-NEXT: shrdl $28, %edx, %ebp
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; X86-NEXT: orl %ebx, %ebp
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; X86-NEXT: jne .LBB0_1
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; X86-NEXT: # %bb.2: # %exit
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; X86-NEXT: movl %edi, (%eax)
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; X86-NEXT: movl %esi, 4(%eax)
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; X86-NEXT: movl %edx, 8(%eax)
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; X86-NEXT: movl %ecx, 12(%eax)
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: popl %ebx
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; X86-NEXT: popl %ebp
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; X86-NEXT: retl $4
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;
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; X64-LABEL: opt_setcc_lt_power_of_2:
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; X64: # %bb.0:
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; X64-NEXT: movq %rsi, %rdx
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: .p2align 4, 0x90
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; X64-NEXT: .LBB0_1: # %loop
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; X64-NEXT: # =>This Inner Loop Header: Depth=1
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; X64-NEXT: addq $1, %rax
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; X64-NEXT: adcq $0, %rdx
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; X64-NEXT: movq %rax, %rcx
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; X64-NEXT: orq %rdx, %rcx
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; X64-NEXT: shrdq $60, %rdx, %rcx
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; X64-NEXT: jne .LBB0_1
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; X64-NEXT: # %bb.2: # %exit
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; X64-NEXT: retq
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br label %loop
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loop:
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%phi.a = phi i128 [ %a, %0 ], [ %inc, %loop ]
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%inc = add i128 %phi.a, 1
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%cmp = icmp ult i128 %inc, 1152921504606846976
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br i1 %cmp, label %exit, label %loop
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exit:
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ret i128 %inc
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}
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define i1 @opt_setcc_srl_eq_zero(i128 %a) nounwind {
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; X86-LABEL: opt_setcc_srl_eq_zero:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: shrdl $17, %ecx, %eax
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; X86-NEXT: orl %esi, %ecx
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; X86-NEXT: shldl $15, %edx, %esi
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; X86-NEXT: orl %esi, %eax
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; X86-NEXT: shrdl $17, %edx, %ecx
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; X86-NEXT: orl %eax, %ecx
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; X86-NEXT: sete %al
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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;
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; X64-LABEL: opt_setcc_srl_eq_zero:
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; X64: # %bb.0:
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; X64-NEXT: orq %rsi, %rdi
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; X64-NEXT: shrdq $17, %rsi, %rdi
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; X64-NEXT: sete %al
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; X64-NEXT: retq
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%srl = lshr i128 %a, 17
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%cmp = icmp eq i128 %srl, 0
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ret i1 %cmp
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}
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define i1 @opt_setcc_srl_ne_zero(i128 %a) nounwind {
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; X86-LABEL: opt_setcc_srl_ne_zero:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: shrdl $17, %ecx, %eax
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; X86-NEXT: orl %esi, %ecx
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; X86-NEXT: shldl $15, %edx, %esi
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; X86-NEXT: orl %esi, %eax
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; X86-NEXT: shrdl $17, %edx, %ecx
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; X86-NEXT: orl %eax, %ecx
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; X86-NEXT: setne %al
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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;
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; X64-LABEL: opt_setcc_srl_ne_zero:
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; X64: # %bb.0:
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; X64-NEXT: orq %rsi, %rdi
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; X64-NEXT: shrdq $17, %rsi, %rdi
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; X64-NEXT: setne %al
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; X64-NEXT: retq
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%srl = lshr i128 %a, 17
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%cmp = icmp ne i128 %srl, 0
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ret i1 %cmp
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}
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define i1 @opt_setcc_shl_eq_zero(i128 %a) nounwind {
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; X86-LABEL: opt_setcc_shl_eq_zero:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: shldl $17, %edx, %esi
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; X86-NEXT: orl %eax, %edx
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; X86-NEXT: shldl $17, %ecx, %edx
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; X86-NEXT: shldl $17, %eax, %ecx
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; X86-NEXT: orl %esi, %ecx
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; X86-NEXT: orl %ecx, %edx
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; X86-NEXT: sete %al
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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;
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; X64-LABEL: opt_setcc_shl_eq_zero:
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; X64: # %bb.0:
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; X64-NEXT: orq %rdi, %rsi
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; X64-NEXT: shldq $17, %rdi, %rsi
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; X64-NEXT: sete %al
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; X64-NEXT: retq
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%shl = shl i128 %a, 17
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%cmp = icmp eq i128 %shl, 0
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ret i1 %cmp
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}
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define i1 @opt_setcc_shl_ne_zero(i128 %a) nounwind {
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; X86-LABEL: opt_setcc_shl_ne_zero:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: shldl $17, %edx, %esi
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; X86-NEXT: orl %eax, %edx
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; X86-NEXT: shldl $17, %ecx, %edx
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; X86-NEXT: shldl $17, %eax, %ecx
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; X86-NEXT: orl %esi, %ecx
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; X86-NEXT: orl %ecx, %edx
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; X86-NEXT: setne %al
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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;
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; X64-LABEL: opt_setcc_shl_ne_zero:
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; X64: # %bb.0:
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; X64-NEXT: orq %rdi, %rsi
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; X64-NEXT: shldq $17, %rdi, %rsi
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; X64-NEXT: setne %al
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; X64-NEXT: retq
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%shl = shl i128 %a, 17
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%cmp = icmp ne i128 %shl, 0
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ret i1 %cmp
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}
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; Negative test: optimization should not be applied if shift has multiple users.
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define i1 @opt_setcc_shl_eq_zero_multiple_shl_users(i128 %a) nounwind {
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; X86-LABEL: opt_setcc_shl_eq_zero_multiple_shl_users:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebx
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: shldl $17, %esi, %edx
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; X86-NEXT: shldl $17, %ecx, %esi
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; X86-NEXT: shldl $17, %eax, %ecx
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; X86-NEXT: shll $17, %eax
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; X86-NEXT: movl %ecx, %edi
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; X86-NEXT: orl %edx, %edi
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; X86-NEXT: movl %eax, %ebx
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; X86-NEXT: orl %esi, %ebx
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; X86-NEXT: orl %edi, %ebx
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; X86-NEXT: sete %bl
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; X86-NEXT: pushl %edx
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; X86-NEXT: pushl %esi
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; X86-NEXT: pushl %ecx
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; X86-NEXT: pushl %eax
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; X86-NEXT: calll use@PLT
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; X86-NEXT: addl $16, %esp
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; X86-NEXT: movl %ebx, %eax
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: popl %ebx
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; X86-NEXT: retl
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;
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; X64-LABEL: opt_setcc_shl_eq_zero_multiple_shl_users:
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; X64: # %bb.0:
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; X64-NEXT: pushq %rbx
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; X64-NEXT: shldq $17, %rdi, %rsi
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; X64-NEXT: shlq $17, %rdi
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: orq %rsi, %rax
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; X64-NEXT: sete %bl
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; X64-NEXT: callq use@PLT
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; X64-NEXT: movl %ebx, %eax
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; X64-NEXT: popq %rbx
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; X64-NEXT: retq
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%shl = shl i128 %a, 17
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%cmp = icmp eq i128 %shl, 0
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call void @use(i128 %shl)
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ret i1 %cmp
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}
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; Check that optimization is applied to DAG having appropriate shape
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; even if there were no actual shift's expansion.
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define i1 @opt_setcc_expanded_shl_correct_shifts(i64 %a, i64 %b) nounwind {
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; X86-LABEL: opt_setcc_expanded_shl_correct_shifts:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: orl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: orl %eax, %edx
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; X86-NEXT: shldl $17, %ecx, %edx
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; X86-NEXT: shldl $17, %eax, %ecx
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; X86-NEXT: orl %edx, %ecx
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; X86-NEXT: sete %al
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; X86-NEXT: retl
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;
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; X64-LABEL: opt_setcc_expanded_shl_correct_shifts:
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; X64: # %bb.0:
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; X64-NEXT: orq %rsi, %rdi
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; X64-NEXT: shldq $17, %rsi, %rdi
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; X64-NEXT: sete %al
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; X64-NEXT: retq
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%shl.a = shl i64 %a, 17
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%srl.b = lshr i64 %b, 47
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%or.0 = or i64 %shl.a, %srl.b
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%shl.b = shl i64 %b, 17
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%or.1 = or i64 %or.0, %shl.b
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%cmp = icmp eq i64 %or.1, 0
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ret i1 %cmp
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}
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; Negative test: optimization should not be applied as
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; constants used in shifts do not match.
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define i1 @opt_setcc_expanded_shl_wrong_shifts(i64 %a, i64 %b) nounwind {
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; X86-LABEL: opt_setcc_expanded_shl_wrong_shifts:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: shldl $17, %edx, %esi
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; X86-NEXT: shldl $17, %ecx, %edx
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; X86-NEXT: shldl $18, %eax, %ecx
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; X86-NEXT: shll $18, %eax
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; X86-NEXT: orl %edx, %eax
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; X86-NEXT: orl %esi, %ecx
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; X86-NEXT: orl %eax, %ecx
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; X86-NEXT: sete %al
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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;
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; X64-LABEL: opt_setcc_expanded_shl_wrong_shifts:
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; X64: # %bb.0:
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; X64-NEXT: shldq $17, %rsi, %rdi
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; X64-NEXT: shlq $18, %rsi
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; X64-NEXT: orq %rdi, %rsi
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; X64-NEXT: sete %al
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; X64-NEXT: retq
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%shl.a = shl i64 %a, 17
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%srl.b = lshr i64 %b, 47
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%or.0 = or i64 %shl.a, %srl.b
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%shl.b = shl i64 %b, 18
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%or.1 = or i64 %or.0, %shl.b
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%cmp = icmp eq i64 %or.1, 0
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ret i1 %cmp
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}
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declare void @use(i128 %a)
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