4a36e96c3f
This simple heuristic uses the estimated live range length combined with the number of registers in the class to switch which heuristic to use. This was taking the raw number of registers in the class, even though not all of them may be available. AMDGPU heavily relies on dynamically reserved numbers of registers based on user attributes to satisfy occupancy constraints, so the raw number is highly misleading. There are still a few problems here. In the original testcase that made me notice this, the live range size is incorrect after the scheduler rearranges instructions, since the instructions don't have the original InstrDist offsets. Additionally, I think it would be more appropriate to use the number of disjointly allocatable registers in the class. For the AMDGPU register tuples, there are a large number of registers in each tuple class, but only a small fraction can actually be allocated at the same time since they all overlap with each other. It seems we do not have a query that corresponds to the number of independently allocatable registers. Relatedly, I'm still debugging some allocation failures where overlapping tuples seem to not be handled correctly. The test changes are mostly noise. There are a handful of x86 tests that look like regressions with an additional spill, and a handful that now avoid a spill. The worst looking regression is likely test/Thumb2/mve-vld4.ll which introduces a few additional spills. test/CodeGen/AMDGPU/soft-clause-exceeds-register-budget.ll shows a massive improvement by completely eliminating a large number of spills inside a loop.
188 lines
7.9 KiB
LLVM
188 lines
7.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86-SSE
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X86-AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX
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define i32 @f(<4 x float> %A, i8* %B, <2 x double> %C, i32 %D, <2 x i64> %E, <4 x i32> %F, <8 x i16> %G, <16 x i8> %H, i64 %I, i32* %loadptr) nounwind {
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; X86-SSE-LABEL: f:
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; X86-SSE: # %bb.0:
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; X86-SSE-NEXT: pushl %ebp
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; X86-SSE-NEXT: movl %esp, %ebp
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; X86-SSE-NEXT: pushl %esi
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; X86-SSE-NEXT: andl $-16, %esp
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; X86-SSE-NEXT: subl $16, %esp
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; X86-SSE-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
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; X86-SSE-NEXT: movl 12(%ebp), %ecx
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; X86-SSE-NEXT: movdqa 56(%ebp), %xmm4
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; X86-SSE-NEXT: movdqa 40(%ebp), %xmm5
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; X86-SSE-NEXT: movdqa 24(%ebp), %xmm6
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; X86-SSE-NEXT: movl 8(%ebp), %esi
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; X86-SSE-NEXT: movl 80(%ebp), %edx
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; X86-SSE-NEXT: movl (%edx), %eax
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; X86-SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
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; X86-SSE-NEXT: movntps %xmm0, (%esi)
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; X86-SSE-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
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; X86-SSE-NEXT: addl (%edx), %eax
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; X86-SSE-NEXT: movntdq %xmm2, (%esi)
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; X86-SSE-NEXT: addpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
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; X86-SSE-NEXT: addl (%edx), %eax
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; X86-SSE-NEXT: movntpd %xmm1, (%esi)
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; X86-SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm6
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; X86-SSE-NEXT: addl (%edx), %eax
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; X86-SSE-NEXT: movntdq %xmm6, (%esi)
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; X86-SSE-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm5
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; X86-SSE-NEXT: addl (%edx), %eax
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; X86-SSE-NEXT: movntdq %xmm5, (%esi)
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; X86-SSE-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm4
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; X86-SSE-NEXT: addl (%edx), %eax
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; X86-SSE-NEXT: movntdq %xmm4, (%esi)
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; X86-SSE-NEXT: addl (%edx), %eax
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; X86-SSE-NEXT: movntil %ecx, (%esi)
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; X86-SSE-NEXT: addl (%edx), %eax
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; X86-SSE-NEXT: movsd %xmm3, (%esi)
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; X86-SSE-NEXT: addl (%edx), %eax
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; X86-SSE-NEXT: leal -4(%ebp), %esp
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; X86-SSE-NEXT: popl %esi
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; X86-SSE-NEXT: popl %ebp
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; X86-SSE-NEXT: retl
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;
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; X86-AVX-LABEL: f:
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; X86-AVX: # %bb.0:
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; X86-AVX-NEXT: pushl %ebp
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; X86-AVX-NEXT: movl %esp, %ebp
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; X86-AVX-NEXT: pushl %esi
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; X86-AVX-NEXT: andl $-16, %esp
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; X86-AVX-NEXT: subl $16, %esp
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; X86-AVX-NEXT: vmovsd {{.*#+}} xmm3 = mem[0],zero
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; X86-AVX-NEXT: movl 12(%ebp), %ecx
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; X86-AVX-NEXT: vmovdqa 56(%ebp), %xmm4
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; X86-AVX-NEXT: vmovdqa 40(%ebp), %xmm5
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; X86-AVX-NEXT: vmovdqa 24(%ebp), %xmm6
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; X86-AVX-NEXT: movl 8(%ebp), %esi
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; X86-AVX-NEXT: movl 80(%ebp), %edx
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; X86-AVX-NEXT: movl (%edx), %eax
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; X86-AVX-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
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; X86-AVX-NEXT: vmovntps %xmm0, (%esi)
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; X86-AVX-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm0
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; X86-AVX-NEXT: addl (%edx), %eax
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; X86-AVX-NEXT: vmovntdq %xmm0, (%esi)
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; X86-AVX-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
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; X86-AVX-NEXT: addl (%edx), %eax
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; X86-AVX-NEXT: vmovntpd %xmm0, (%esi)
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; X86-AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm6, %xmm0
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; X86-AVX-NEXT: addl (%edx), %eax
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; X86-AVX-NEXT: vmovntdq %xmm0, (%esi)
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; X86-AVX-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm5, %xmm0
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; X86-AVX-NEXT: addl (%edx), %eax
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; X86-AVX-NEXT: vmovntdq %xmm0, (%esi)
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; X86-AVX-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm4, %xmm0
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; X86-AVX-NEXT: addl (%edx), %eax
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; X86-AVX-NEXT: vmovntdq %xmm0, (%esi)
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; X86-AVX-NEXT: addl (%edx), %eax
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; X86-AVX-NEXT: movntil %ecx, (%esi)
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; X86-AVX-NEXT: addl (%edx), %eax
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; X86-AVX-NEXT: vmovsd %xmm3, (%esi)
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; X86-AVX-NEXT: addl (%edx), %eax
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; X86-AVX-NEXT: leal -4(%ebp), %esp
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; X86-AVX-NEXT: popl %esi
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; X86-AVX-NEXT: popl %ebp
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; X86-AVX-NEXT: retl
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;
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; X64-SSE-LABEL: f:
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; X64-SSE: # %bb.0:
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; X64-SSE-NEXT: movl (%rcx), %eax
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; X64-SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; X64-SSE-NEXT: movntps %xmm0, (%rdi)
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; X64-SSE-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
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; X64-SSE-NEXT: addl (%rcx), %eax
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; X64-SSE-NEXT: movntdq %xmm2, (%rdi)
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; X64-SSE-NEXT: addpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
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; X64-SSE-NEXT: addl (%rcx), %eax
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; X64-SSE-NEXT: movntpd %xmm1, (%rdi)
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; X64-SSE-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
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; X64-SSE-NEXT: addl (%rcx), %eax
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; X64-SSE-NEXT: movntdq %xmm3, (%rdi)
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; X64-SSE-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4
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; X64-SSE-NEXT: addl (%rcx), %eax
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; X64-SSE-NEXT: movntdq %xmm4, (%rdi)
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; X64-SSE-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5
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; X64-SSE-NEXT: addl (%rcx), %eax
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; X64-SSE-NEXT: movntdq %xmm5, (%rdi)
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; X64-SSE-NEXT: addl (%rcx), %eax
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; X64-SSE-NEXT: movntil %esi, (%rdi)
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; X64-SSE-NEXT: addl (%rcx), %eax
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; X64-SSE-NEXT: movntiq %rdx, (%rdi)
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; X64-SSE-NEXT: addl (%rcx), %eax
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; X64-SSE-NEXT: retq
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;
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; X64-AVX-LABEL: f:
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; X64-AVX: # %bb.0:
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; X64-AVX-NEXT: movl (%rcx), %eax
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; X64-AVX-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; X64-AVX-NEXT: vmovntps %xmm0, (%rdi)
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; X64-AVX-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
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; X64-AVX-NEXT: addl (%rcx), %eax
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; X64-AVX-NEXT: vmovntdq %xmm0, (%rdi)
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; X64-AVX-NEXT: vaddpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
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; X64-AVX-NEXT: addl (%rcx), %eax
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; X64-AVX-NEXT: vmovntpd %xmm0, (%rdi)
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; X64-AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm0
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; X64-AVX-NEXT: addl (%rcx), %eax
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; X64-AVX-NEXT: vmovntdq %xmm0, (%rdi)
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; X64-AVX-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4, %xmm0
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; X64-AVX-NEXT: addl (%rcx), %eax
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; X64-AVX-NEXT: vmovntdq %xmm0, (%rdi)
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; X64-AVX-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5, %xmm0
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; X64-AVX-NEXT: addl (%rcx), %eax
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; X64-AVX-NEXT: vmovntdq %xmm0, (%rdi)
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; X64-AVX-NEXT: addl (%rcx), %eax
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; X64-AVX-NEXT: movntil %esi, (%rdi)
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; X64-AVX-NEXT: addl (%rcx), %eax
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; X64-AVX-NEXT: movntiq %rdx, (%rdi)
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; X64-AVX-NEXT: addl (%rcx), %eax
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; X64-AVX-NEXT: retq
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%v0 = load i32, i32* %loadptr, align 1
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%cast = bitcast i8* %B to <4 x float>*
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%A2 = fadd <4 x float> %A, <float 1.0, float 2.0, float 3.0, float 4.0>
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store <4 x float> %A2, <4 x float>* %cast, align 16, !nontemporal !0
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%v1 = load i32, i32* %loadptr, align 1
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%cast1 = bitcast i8* %B to <2 x i64>*
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%E2 = add <2 x i64> %E, <i64 1, i64 2>
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store <2 x i64> %E2, <2 x i64>* %cast1, align 16, !nontemporal !0
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%v2 = load i32, i32* %loadptr, align 1
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%cast2 = bitcast i8* %B to <2 x double>*
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%C2 = fadd <2 x double> %C, <double 1.0, double 2.0>
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store <2 x double> %C2, <2 x double>* %cast2, align 16, !nontemporal !0
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%v3 = load i32, i32* %loadptr, align 1
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%cast3 = bitcast i8* %B to <4 x i32>*
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%F2 = add <4 x i32> %F, <i32 1, i32 2, i32 3, i32 4>
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store <4 x i32> %F2, <4 x i32>* %cast3, align 16, !nontemporal !0
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%v4 = load i32, i32* %loadptr, align 1
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%cast4 = bitcast i8* %B to <8 x i16>*
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%G2 = add <8 x i16> %G, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
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store <8 x i16> %G2, <8 x i16>* %cast4, align 16, !nontemporal !0
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%v5 = load i32, i32* %loadptr, align 1
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%cast5 = bitcast i8* %B to <16 x i8>*
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%H2 = add <16 x i8> %H, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
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store <16 x i8> %H2, <16 x i8>* %cast5, align 16, !nontemporal !0
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%v6 = load i32, i32* %loadptr, align 1
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%cast6 = bitcast i8* %B to i32*
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store i32 %D, i32* %cast6, align 1, !nontemporal !0
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%v7 = load i32, i32* %loadptr, align 1
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%cast7 = bitcast i8* %B to i64*
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store i64 %I, i64* %cast7, align 1, !nontemporal !0
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%v8 = load i32, i32* %loadptr, align 1
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%sum1 = add i32 %v0, %v1
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%sum2 = add i32 %sum1, %v2
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%sum3 = add i32 %sum2, %v3
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%sum4 = add i32 %sum3, %v4
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%sum5 = add i32 %sum4, %v5
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%sum6 = add i32 %sum5, %v6
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%sum7 = add i32 %sum6, %v7
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%sum8 = add i32 %sum7, %v8
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ret i32 %sum8
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}
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!0 = !{i32 1}
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