c486b82cfb
This is a retry of b4b97ec813a0 - that was reverted because it could cause miscompiles by illegally reordering memory operations. A new test based on #53695 is added here to verify we do not have that same problem. extract_vec_elt (load X), C --> scalar load (X+C) As noted in the comment, DAGCombiner has this fold -- and the code in this patch is adapted from DAGCombiner::scalarizeExtractedVectorLoad() -- but x86 should benefit even if the loaded vector has other uses as long as we apply some other x86-specific conditions. The motivating example from #50310 is shown in vec_int_to_fp.ll. Fixes #50310 Fixes #53695 Differential Revision: https://reviews.llvm.org/D118376
106 lines
3.5 KiB
LLVM
106 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse2 | FileCheck %s --check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s --check-prefix=SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512bw | FileCheck %s --check-prefix=AVX
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declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)
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define i1 @parseHeaders(i64 * %ptr) nounwind {
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; SSE2-LABEL: parseHeaders:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movdqu (%rdi), %xmm0
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
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; SSE2-NEXT: pmovmskb %xmm1, %eax
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; SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
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; SSE2-NEXT: sete %al
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: parseHeaders:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movdqu (%rdi), %xmm0
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; SSE41-NEXT: ptest %xmm0, %xmm0
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; SSE41-NEXT: sete %al
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: parseHeaders:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovdqu (%rdi), %xmm0
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; AVX-NEXT: vptest %xmm0, %xmm0
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; AVX-NEXT: sete %al
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; AVX-NEXT: retq
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%vptr = bitcast i64 * %ptr to <2 x i64> *
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%vload = load <2 x i64>, <2 x i64> * %vptr, align 8
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%vreduce = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %vload)
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%vcheck = icmp eq i64 %vreduce, 0
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ret i1 %vcheck
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}
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define i1 @parseHeaders2_scalar_or(i64 * %ptr) nounwind {
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; SSE2-LABEL: parseHeaders2_scalar_or:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movdqu (%rdi), %xmm0
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqb %xmm0, %xmm1
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; SSE2-NEXT: pmovmskb %xmm1, %eax
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; SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
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; SSE2-NEXT: sete %al
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: parseHeaders2_scalar_or:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movdqu (%rdi), %xmm0
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; SSE41-NEXT: ptest %xmm0, %xmm0
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; SSE41-NEXT: sete %al
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: parseHeaders2_scalar_or:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovdqu (%rdi), %xmm0
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; AVX-NEXT: vptest %xmm0, %xmm0
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; AVX-NEXT: sete %al
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; AVX-NEXT: retq
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%vptr = bitcast i64 * %ptr to <2 x i64> *
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%vload = load <2 x i64>, <2 x i64> * %vptr, align 8
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%v1 = extractelement <2 x i64> %vload, i32 0
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%v2 = extractelement <2 x i64> %vload, i32 1
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%vreduce = or i64 %v1, %v2
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%vcheck = icmp eq i64 %vreduce, 0
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ret i1 %vcheck
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}
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define i1 @parseHeaders2_scalar_and(i64 * %ptr) nounwind {
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; SSE2-LABEL: parseHeaders2_scalar_and:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movdqu (%rdi), %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
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; SSE2-NEXT: movq %xmm0, %rax
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; SSE2-NEXT: testq %rax, (%rdi)
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; SSE2-NEXT: sete %al
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: parseHeaders2_scalar_and:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movq (%rdi), %rax
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; SSE41-NEXT: testq %rax, 8(%rdi)
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; SSE41-NEXT: sete %al
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: parseHeaders2_scalar_and:
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; AVX: # %bb.0:
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; AVX-NEXT: movq (%rdi), %rax
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; AVX-NEXT: testq %rax, 8(%rdi)
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; AVX-NEXT: sete %al
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; AVX-NEXT: retq
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%vptr = bitcast i64 * %ptr to <2 x i64> *
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%vload = load <2 x i64>, <2 x i64> * %vptr, align 8
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%v1 = extractelement <2 x i64> %vload, i32 0
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%v2 = extractelement <2 x i64> %vload, i32 1
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%vreduce = and i64 %v1, %v2
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%vcheck = icmp eq i64 %vreduce, 0
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ret i1 %vcheck
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}
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