b81e26c7f4
This time with the right bug number. When we rewrite the setcc we replace set old setcc output register with the new CondReg. But since CondReg can be shared by other replacements, we don't know if the kill flags for the old register are valid for CondReg. So be conservative and remove them. The test case has a SETCCr and a SETCCm on the same condition so they end up sharing the same CondReg. The SETCCr had one use with a kill flag. This kill flag isn't valid after the replacement because CondReg needs a live range extending to the later SETCCm replacment. Fixes PR51903.
109 lines
4.6 KiB
YAML
109 lines
4.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc %s -o - -mtriple=x86_64-unknown-linux-gnu -run-pass=x86-flags-copy-lowering -verify-machineinstrs | FileCheck %s
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--- |
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; ModuleID = 'bugpoint-reduced-simplified.ll'
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source_filename = "test.c"
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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@a = external global i32, align 4
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declare void @e()
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define void @f() {
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%0 = load i32, i32* @a, align 4
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%conv = sext i32 %0 to i64
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%1 = load i64, i64* undef, align 8
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%or = or i64 %1, %conv
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store i64 %or, i64* undef, align 8
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call void @e()
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%cmp4 = icmp eq i64 %or, 0
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%conv5 = zext i1 %cmp4 to i32
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%conv6 = trunc i32 %conv5 to i8
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store i8 %conv6, i8* undef, align 1
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%conv7 = sext i8 %conv6 to i32
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%bf.cast = trunc i40 undef to i32
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%xor = xor i32 %conv7, %bf.cast
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%conv8 = sext i32 %xor to i64
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store i64 %conv8, i64* undef, align 8
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br label %for.body
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}
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...
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---
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name: f
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alignment: 16
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr64 }
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- { id: 1, class: gr64 }
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- { id: 2, class: gr32 }
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- { id: 3, class: gr64 }
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- { id: 4, class: gr32 }
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- { id: 5, class: gr32 }
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- { id: 6, class: gr32 }
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- { id: 7, class: gr64 }
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- { id: 8, class: gr64 }
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- { id: 9, class: gr64 }
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- { id: 10, class: gr64 }
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- { id: 11, class: gr8 }
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- { id: 12, class: gr64 }
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frameInfo:
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maxAlignment: 1
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hasCalls: true
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: f
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: JMP_1 %bb.1
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; CHECK: bb.1.for.body:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @a, $noreg :: (load (s64) from got)
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; CHECK: [[MOVSX64rm32_:%[0-9]+]]:gr64 = MOVSX64rm32 killed [[MOV64rm]], 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from @a)
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; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
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; CHECK: OR64mr [[DEF]], 1, $noreg, 0, $noreg, [[MOVSX64rm32_]], implicit-def $eflags :: (store (s64) into `i64* undef`), (load (s64) from `i64* undef`)
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; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
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; CHECK: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
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; CHECK: CALL64pcrel32 target-flags(x86-plt) @e, csr_64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp
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; CHECK: ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
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; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
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; CHECK: [[DEF1:%[0-9]+]]:gr64 = IMPLICIT_DEF
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; CHECK: MOV8mr [[DEF1]], 1, $noreg, 0, $noreg, [[SETCCr]] :: (store (s8) into `i8* undef`)
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; CHECK: [[DEF2:%[0-9]+]]:gr32 = IMPLICIT_DEF
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; CHECK: [[XOR32rr:%[0-9]+]]:gr32 = XOR32rr [[MOVZX32rr8_]], [[DEF2]], implicit-def $eflags
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; CHECK: [[MOVSX64rr32_:%[0-9]+]]:gr64 = MOVSX64rr32 [[XOR32rr]]
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; CHECK: [[DEF3:%[0-9]+]]:gr64 = IMPLICIT_DEF
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; CHECK: MOV64mr [[DEF3]], 1, $noreg, 0, $noreg, [[MOVSX64rr32_]] :: (store (s64) into `i64* undef`)
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; CHECK: JMP_1 %bb.1
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bb.0.entry:
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JMP_1 %bb.1
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bb.1.for.body:
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%7:gr64 = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @a, $noreg :: (load (s64) from got)
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%8:gr64 = MOVSX64rm32 killed %7, 1, $noreg, 0, $noreg :: (dereferenceable load (s32) from @a)
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%9:gr64 = IMPLICIT_DEF
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OR64mr %9, 1, $noreg, 0, $noreg, %8, implicit-def $eflags :: (store (s64) into `i64* undef`), (load (s64) from `i64* undef`)
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%10:gr64 = COPY $eflags
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ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
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CALL64pcrel32 target-flags(x86-plt) @e, csr_64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp
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ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp
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$eflags = COPY %10
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%11:gr8 = SETCCr 4, implicit $eflags
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%4:gr32 = MOVZX32rr8 killed %11
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%12:gr64 = IMPLICIT_DEF
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SETCCm %12, 1, $noreg, 0, $noreg, 4, implicit $eflags :: (store (s8) into `i8* undef`)
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%5:gr32 = IMPLICIT_DEF
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%6:gr32 = XOR32rr %4, %5, implicit-def $eflags
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%3:gr64 = MOVSX64rr32 %6
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%0:gr64 = IMPLICIT_DEF
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MOV64mr %0, 1, $noreg, 0, $noreg, %3 :: (store (s64) into `i64* undef`)
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JMP_1 %bb.1
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...
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