f1d8345a2a
Currently we create register mappings for registers used only once in current
MBB. For registers with multiple uses, when all the uses are in the current MBB,
we can also create mappings for them similarly according to the last use.
For example
%reg101 = ...
= ... reg101
%reg103 = ADD %reg101, %reg102
We can create mapping between %reg101 and %reg103.
Differential Revision: https://reviews.llvm.org/D113193
196 lines
7.7 KiB
LLVM
196 lines
7.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,AVX512
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=AVX,AVX512
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefixes=AVX,AVX512
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; AVX1 has support for 256-bit bitwise logic because the FP variants were included.
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; If using those ops requires extra insert/extract though, it's probably not worth it.
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define <8 x i32> @PR32790(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) {
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; SSE-LABEL: PR32790:
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; SSE: # %bb.0:
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; SSE-NEXT: paddd %xmm2, %xmm0
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; SSE-NEXT: paddd %xmm3, %xmm1
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; SSE-NEXT: pand %xmm5, %xmm1
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; SSE-NEXT: pand %xmm4, %xmm0
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; SSE-NEXT: psubd %xmm6, %xmm0
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; SSE-NEXT: psubd %xmm7, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: PR32790:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm4
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
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; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm1
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; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm1
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; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vpand %xmm2, %xmm4, %xmm1
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; AVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm1
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: PR32790:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0
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; AVX2-NEXT: vpsubd %ymm3, %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: PR32790:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpaddd %ymm1, %ymm0, %ymm0
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; AVX512-NEXT: vpand %ymm2, %ymm0, %ymm0
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; AVX512-NEXT: vpsubd %ymm3, %ymm0, %ymm0
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; AVX512-NEXT: retq
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%add = add <8 x i32> %a, %b
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%and = and <8 x i32> %add, %c
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%sub = sub <8 x i32> %and, %d
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ret <8 x i32> %sub
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}
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; In a more extreme case, even the later AVX targets should avoid extract/insert just
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; because 256-bit ops are supported.
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define <4 x i32> @do_not_use_256bit_op(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
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; SSE-LABEL: do_not_use_256bit_op:
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; SSE: # %bb.0:
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; SSE-NEXT: pand %xmm2, %xmm0
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; SSE-NEXT: pand %xmm3, %xmm1
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; SSE-NEXT: psubd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: do_not_use_256bit_op:
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; AVX: # %bb.0:
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; AVX-NEXT: vpand %xmm2, %xmm0, %xmm0
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; AVX-NEXT: vpand %xmm3, %xmm1, %xmm1
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; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%concat1 = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%concat2 = shufflevector <4 x i32> %c, <4 x i32> %d, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%and = and <8 x i32> %concat1, %concat2
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%extract1 = shufflevector <8 x i32> %and, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%extract2 = shufflevector <8 x i32> %and, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%sub = sub <4 x i32> %extract1, %extract2
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ret <4 x i32> %sub
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}
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; When extracting from a vector binop, the source width should be a multiple of the destination width.
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; https://bugs.llvm.org/show_bug.cgi?id=39511
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define <3 x float> @PR39511(<4 x float> %t0, <3 x float>* %b) {
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; SSE-LABEL: PR39511:
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; SSE: # %bb.0:
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; SSE-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: PR39511:
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; AVX: # %bb.0:
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; AVX-NEXT: vaddps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%add = fadd <4 x float> %t0, <float 1.0, float 2.0, float 3.0, float 4.0>
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%ext = shufflevector <4 x float> %add, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
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ret <3 x float> %ext
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}
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; When extracting from a vector binop, we need to be extracting
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; by a width of at least 1 of the original vector elements.
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; https://bugs.llvm.org/show_bug.cgi?id=39893
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define <2 x i8> @PR39893(<2 x i32> %x, <8 x i8> %y) {
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; SSE-LABEL: PR39893:
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; SSE: # %bb.0:
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; SSE-NEXT: pxor %xmm2, %xmm2
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; SSE-NEXT: psubd %xmm0, %xmm2
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; SSE-NEXT: psrld $16, %xmm2
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
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; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
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; SSE-NEXT: movdqa %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: PR39893:
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; AVX: # %bb.0:
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; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vpsubd %xmm0, %xmm2, %xmm0
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; AVX-NEXT: vpsrld $16, %xmm0, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
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; AVX-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
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; AVX-NEXT: retq
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%sub = sub <2 x i32> <i32 0, i32 undef>, %x
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%bc = bitcast <2 x i32> %sub to <8 x i8>
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%shuffle = shufflevector <8 x i8> %y, <8 x i8> %bc, <2 x i32> <i32 10, i32 4>
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ret <2 x i8> %shuffle
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}
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define <2 x i8> @PR39893_2(<2 x float> %x) {
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; SSE-LABEL: PR39893_2:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm1, %xmm1
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; SSE-NEXT: subps %xmm0, %xmm1
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: PR39893_2:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vsubps %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%fsub = fsub <2 x float> zeroinitializer, %x
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%bc = bitcast <2 x float> %fsub to <8 x i8>
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%shuffle = shufflevector <8 x i8> %bc, <8 x i8> undef, <2 x i32> <i32 0, i32 1>
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ret <2 x i8> %shuffle
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}
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define <4 x double> @fmul_v2f64(<2 x double> %x, <2 x double> %y) {
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; SSE-LABEL: fmul_v2f64:
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; SSE: # %bb.0:
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; SSE-NEXT: movapd %xmm1, %xmm2
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; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm0[0]
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; SSE-NEXT: mulpd %xmm2, %xmm2
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; SSE-NEXT: mulpd %xmm1, %xmm1
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; SSE-NEXT: addpd %xmm1, %xmm2
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; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
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; SSE-NEXT: movapd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: fmul_v2f64:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm1[0],xmm0[0]
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; AVX1-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
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; AVX1-NEXT: vmulpd %xmm0, %xmm0, %xmm0
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; AVX1-NEXT: vmulpd %xmm2, %xmm2, %xmm1
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; AVX1-NEXT: vaddpd %xmm0, %xmm1, %xmm0
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; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: fmul_v2f64:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm1[0],xmm0[0]
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; AVX2-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
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; AVX2-NEXT: vmulpd %xmm0, %xmm0, %xmm0
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; AVX2-NEXT: vmulpd %xmm2, %xmm2, %xmm1
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; AVX2-NEXT: vaddpd %xmm0, %xmm1, %xmm0
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; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: fmul_v2f64:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vunpckhpd {{.*#+}} xmm2 = xmm0[1],xmm1[1]
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; AVX512-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0]
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; AVX512-NEXT: vmulpd %xmm0, %xmm0, %xmm0
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; AVX512-NEXT: vfmadd231pd {{.*#+}} xmm0 = (xmm2 * xmm2) + xmm0
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; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
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; AVX512-NEXT: retq
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%s = shufflevector <2 x double> %x, <2 x double> %y, <4 x i32> <i32 2, i32 0, i32 1, i32 3>
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%bo = fmul fast <4 x double> %s, %s
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%ext = shufflevector <4 x double> %bo, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%add = fadd fast <4 x double> %bo, %ext
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%rdx = shufflevector <4 x double> %add, <4 x double> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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ret <4 x double> %rdx
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}
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