0aef747b84
The motivation is that the update script has at least two deviations (`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from what pretty much all the checklines were generated with, and most of the tests are still not updated, so each time one of the non-up-to-date tests is updated to see the effect of the code change, there is a lot of noise. Instead of having to deal with that each time, let's just deal with everything at once. This has been done via: ``` cd llvm-project/llvm/test/CodeGen/X86 grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc ``` Not all tests were regenerated, however.
395 lines
13 KiB
LLVM
395 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64
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; Test based on pr5626 to load/store
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;
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%i32vec3 = type <3 x i32>
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define void @add3i32(%i32vec3* sret(%i32vec3) %ret, %i32vec3* %ap, %i32vec3* %bp) {
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; X86-LABEL: add3i32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movdqa (%edx), %xmm0
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; X86-NEXT: paddd (%ecx), %xmm0
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; X86-NEXT: pextrd $2, %xmm0, 8(%eax)
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; X86-NEXT: pextrd $1, %xmm0, 4(%eax)
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; X86-NEXT: movd %xmm0, (%eax)
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; X86-NEXT: retl $4
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;
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; X64-LABEL: add3i32:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: movdqa (%rsi), %xmm0
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; X64-NEXT: paddd (%rdx), %xmm0
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; X64-NEXT: pextrd $2, %xmm0, 8(%rdi)
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; X64-NEXT: movq %xmm0, (%rdi)
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; X64-NEXT: retq
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%a = load %i32vec3, %i32vec3* %ap, align 16
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%b = load %i32vec3, %i32vec3* %bp, align 16
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%x = add %i32vec3 %a, %b
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store %i32vec3 %x, %i32vec3* %ret, align 16
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ret void
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}
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define void @add3i32_2(%i32vec3* sret(%i32vec3) %ret, %i32vec3* %ap, %i32vec3* %bp) {
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; X86-LABEL: add3i32_2:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X86-NEXT: pinsrd $1, 4(%edx), %xmm0
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; X86-NEXT: pinsrd $2, 8(%edx), %xmm0
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; X86-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X86-NEXT: pinsrd $1, 4(%ecx), %xmm1
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; X86-NEXT: pinsrd $2, 8(%ecx), %xmm1
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; X86-NEXT: paddd %xmm0, %xmm1
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; X86-NEXT: movd %xmm1, (%eax)
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; X86-NEXT: pextrd $1, %xmm1, 4(%eax)
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; X86-NEXT: pextrd $2, %xmm1, 8(%eax)
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; X86-NEXT: retl $4
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;
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; X64-LABEL: add3i32_2:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; X64-NEXT: pinsrd $2, 8(%rsi), %xmm0
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; X64-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
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; X64-NEXT: pinsrd $2, 8(%rdx), %xmm1
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; X64-NEXT: paddd %xmm0, %xmm1
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; X64-NEXT: pextrd $2, %xmm1, 8(%rdi)
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; X64-NEXT: movq %xmm1, (%rdi)
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; X64-NEXT: retq
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%a = load %i32vec3, %i32vec3* %ap, align 8
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%b = load %i32vec3, %i32vec3* %bp, align 8
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%x = add %i32vec3 %a, %b
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store %i32vec3 %x, %i32vec3* %ret, align 8
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ret void
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}
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%i32vec7 = type <7 x i32>
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define void @add7i32(%i32vec7* sret(%i32vec7) %ret, %i32vec7* %ap, %i32vec7* %bp) {
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; X86-LABEL: add7i32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movdqa (%edx), %xmm0
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; X86-NEXT: movdqa 16(%edx), %xmm1
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; X86-NEXT: paddd (%ecx), %xmm0
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; X86-NEXT: paddd 16(%ecx), %xmm1
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; X86-NEXT: movd %xmm1, 16(%eax)
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; X86-NEXT: pextrd $1, %xmm1, 20(%eax)
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; X86-NEXT: pextrd $2, %xmm1, 24(%eax)
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; X86-NEXT: movdqa %xmm0, (%eax)
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; X86-NEXT: retl $4
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;
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; X64-LABEL: add7i32:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: movdqa (%rsi), %xmm0
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; X64-NEXT: movdqa 16(%rsi), %xmm1
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; X64-NEXT: paddd (%rdx), %xmm0
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; X64-NEXT: paddd 16(%rdx), %xmm1
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; X64-NEXT: movq %xmm1, 16(%rdi)
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; X64-NEXT: pextrd $2, %xmm1, 24(%rdi)
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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%a = load %i32vec7, %i32vec7* %ap, align 16
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%b = load %i32vec7, %i32vec7* %bp, align 16
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%x = add %i32vec7 %a, %b
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store %i32vec7 %x, %i32vec7* %ret, align 16
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ret void
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}
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%i32vec12 = type <12 x i32>
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define void @add12i32(%i32vec12* sret(%i32vec12) %ret, %i32vec12* %ap, %i32vec12* %bp) {
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; X86-LABEL: add12i32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movdqa 32(%edx), %xmm0
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; X86-NEXT: movdqa (%edx), %xmm1
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; X86-NEXT: movdqa 16(%edx), %xmm2
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; X86-NEXT: paddd (%ecx), %xmm1
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; X86-NEXT: paddd 32(%ecx), %xmm0
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; X86-NEXT: paddd 16(%ecx), %xmm2
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; X86-NEXT: movdqa %xmm2, 16(%eax)
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; X86-NEXT: movdqa %xmm0, 32(%eax)
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; X86-NEXT: movdqa %xmm1, (%eax)
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; X86-NEXT: retl $4
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;
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; X64-LABEL: add12i32:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: movdqa (%rsi), %xmm0
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; X64-NEXT: movdqa 16(%rsi), %xmm1
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; X64-NEXT: movdqa 32(%rsi), %xmm2
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; X64-NEXT: paddd (%rdx), %xmm0
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; X64-NEXT: paddd 32(%rdx), %xmm2
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; X64-NEXT: paddd 16(%rdx), %xmm1
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; X64-NEXT: movdqa %xmm1, 16(%rdi)
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; X64-NEXT: movdqa %xmm2, 32(%rdi)
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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%a = load %i32vec12, %i32vec12* %ap, align 16
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%b = load %i32vec12, %i32vec12* %bp, align 16
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%x = add %i32vec12 %a, %b
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store %i32vec12 %x, %i32vec12* %ret, align 16
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ret void
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}
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%i16vec3 = type <3 x i16>
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define void @add3i16(%i16vec3* nocapture sret(%i16vec3) %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind {
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; X86-LABEL: add3i16:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X86-NEXT: pinsrw $2, 4(%edx), %xmm0
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; X86-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X86-NEXT: pinsrw $2, 4(%ecx), %xmm1
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; X86-NEXT: paddw %xmm0, %xmm1
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; X86-NEXT: pextrw $2, %xmm1, 4(%eax)
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; X86-NEXT: movd %xmm1, (%eax)
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; X86-NEXT: retl $4
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;
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; X64-LABEL: add3i16:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; X64-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
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; X64-NEXT: paddw %xmm0, %xmm1
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; X64-NEXT: pextrw $2, %xmm1, 4(%rdi)
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; X64-NEXT: movd %xmm1, (%rdi)
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; X64-NEXT: retq
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%a = load %i16vec3, %i16vec3* %ap, align 16
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%b = load %i16vec3, %i16vec3* %bp, align 16
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%x = add %i16vec3 %a, %b
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store %i16vec3 %x, %i16vec3* %ret, align 16
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ret void
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}
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%i16vec4 = type <4 x i16>
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define void @add4i16(%i16vec4* nocapture sret(%i16vec4) %ret, %i16vec4* %ap, %i16vec4* %bp) nounwind {
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; X86-LABEL: add4i16:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; X86-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
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; X86-NEXT: paddw %xmm0, %xmm1
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; X86-NEXT: movq %xmm1, (%eax)
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; X86-NEXT: retl $4
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;
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; X64-LABEL: add4i16:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; X64-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
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; X64-NEXT: paddw %xmm0, %xmm1
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; X64-NEXT: movq %xmm1, (%rdi)
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; X64-NEXT: retq
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%a = load %i16vec4, %i16vec4* %ap, align 16
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%b = load %i16vec4, %i16vec4* %bp, align 16
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%x = add %i16vec4 %a, %b
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store %i16vec4 %x, %i16vec4* %ret, align 16
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ret void
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}
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%i16vec12 = type <12 x i16>
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define void @add12i16(%i16vec12* nocapture sret(%i16vec12) %ret, %i16vec12* %ap, %i16vec12* %bp) nounwind {
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; X86-LABEL: add12i16:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movdqa (%edx), %xmm0
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; X86-NEXT: movdqa 16(%edx), %xmm1
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; X86-NEXT: paddw (%ecx), %xmm0
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; X86-NEXT: paddw 16(%ecx), %xmm1
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; X86-NEXT: movd %xmm1, 16(%eax)
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; X86-NEXT: pextrd $1, %xmm1, 20(%eax)
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; X86-NEXT: movdqa %xmm0, (%eax)
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; X86-NEXT: retl $4
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;
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; X64-LABEL: add12i16:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: movdqa (%rsi), %xmm0
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; X64-NEXT: movdqa 16(%rsi), %xmm1
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; X64-NEXT: paddw (%rdx), %xmm0
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; X64-NEXT: paddw 16(%rdx), %xmm1
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; X64-NEXT: movq %xmm1, 16(%rdi)
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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%a = load %i16vec12, %i16vec12* %ap, align 16
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%b = load %i16vec12, %i16vec12* %bp, align 16
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%x = add %i16vec12 %a, %b
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store %i16vec12 %x, %i16vec12* %ret, align 16
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ret void
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}
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%i16vec18 = type <18 x i16>
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define void @add18i16(%i16vec18* nocapture sret(%i16vec18) %ret, %i16vec18* %ap, %i16vec18* %bp) nounwind {
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; X86-LABEL: add18i16:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movdqa 32(%edx), %xmm0
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; X86-NEXT: movdqa (%edx), %xmm1
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; X86-NEXT: movdqa 16(%edx), %xmm2
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; X86-NEXT: paddw (%ecx), %xmm1
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; X86-NEXT: paddw 32(%ecx), %xmm0
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; X86-NEXT: paddw 16(%ecx), %xmm2
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; X86-NEXT: movdqa %xmm2, 16(%eax)
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; X86-NEXT: movd %xmm0, 32(%eax)
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; X86-NEXT: movdqa %xmm1, (%eax)
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; X86-NEXT: retl $4
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;
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; X64-LABEL: add18i16:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: movdqa (%rsi), %xmm0
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; X64-NEXT: movdqa 16(%rsi), %xmm1
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; X64-NEXT: movdqa 32(%rsi), %xmm2
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; X64-NEXT: paddw (%rdx), %xmm0
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; X64-NEXT: paddw 32(%rdx), %xmm2
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; X64-NEXT: paddw 16(%rdx), %xmm1
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; X64-NEXT: movdqa %xmm1, 16(%rdi)
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; X64-NEXT: movd %xmm2, 32(%rdi)
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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%a = load %i16vec18, %i16vec18* %ap, align 16
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%b = load %i16vec18, %i16vec18* %bp, align 16
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%x = add %i16vec18 %a, %b
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store %i16vec18 %x, %i16vec18* %ret, align 16
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ret void
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}
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%i8vec3 = type <3 x i8>
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define void @add3i8(%i8vec3* nocapture sret(%i8vec3) %ret, %i8vec3* %ap, %i8vec3* %bp) nounwind {
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; X86-LABEL: add3i8:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X86-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X86-NEXT: paddb %xmm0, %xmm1
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; X86-NEXT: pextrb $2, %xmm1, 2(%eax)
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; X86-NEXT: pextrw $0, %xmm1, (%eax)
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; X86-NEXT: retl $4
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;
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; X64-LABEL: add3i8:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X64-NEXT: paddb %xmm0, %xmm1
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; X64-NEXT: pextrb $2, %xmm1, 2(%rdi)
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; X64-NEXT: pextrw $0, %xmm1, (%rdi)
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; X64-NEXT: retq
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%a = load %i8vec3, %i8vec3* %ap, align 16
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%b = load %i8vec3, %i8vec3* %bp, align 16
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%x = add %i8vec3 %a, %b
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store %i8vec3 %x, %i8vec3* %ret, align 16
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ret void
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}
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%i8vec31 = type <31 x i8>
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define void @add31i8(%i8vec31* nocapture sret(%i8vec31) %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind {
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; X86-LABEL: add31i8:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movdqa (%edx), %xmm0
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; X86-NEXT: movdqa 16(%edx), %xmm1
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; X86-NEXT: paddb (%ecx), %xmm0
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; X86-NEXT: paddb 16(%ecx), %xmm1
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; X86-NEXT: movd %xmm1, 16(%eax)
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; X86-NEXT: pextrd $1, %xmm1, 20(%eax)
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; X86-NEXT: pextrd $2, %xmm1, 24(%eax)
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; X86-NEXT: pextrw $6, %xmm1, 28(%eax)
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; X86-NEXT: pextrb $14, %xmm1, 30(%eax)
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; X86-NEXT: movdqa %xmm0, (%eax)
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; X86-NEXT: retl $4
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;
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; X64-LABEL: add31i8:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: movdqa (%rsi), %xmm0
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; X64-NEXT: movdqa 16(%rsi), %xmm1
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; X64-NEXT: paddb (%rdx), %xmm0
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; X64-NEXT: paddb 16(%rdx), %xmm1
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; X64-NEXT: movq %xmm1, 16(%rdi)
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; X64-NEXT: pextrd $2, %xmm1, 24(%rdi)
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; X64-NEXT: pextrw $6, %xmm1, 28(%rdi)
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; X64-NEXT: pextrb $14, %xmm1, 30(%rdi)
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; X64-NEXT: movdqa %xmm0, (%rdi)
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|
; X64-NEXT: retq
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|
%a = load %i8vec31, %i8vec31* %ap, align 16
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|
%b = load %i8vec31, %i8vec31* %bp, align 16
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%x = add %i8vec31 %a, %b
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|
store %i8vec31 %x, %i8vec31* %ret, align 16
|
|
ret void
|
|
}
|
|
|
|
|
|
%i8vec3pack = type { <3 x i8>, i8 }
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define void @rot(%i8vec3pack* nocapture sret(%i8vec3pack) %result, %i8vec3pack* %X, %i8vec3pack* %rot) nounwind {
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|
; X86-LABEL: rot:
|
|
; X86: # %bb.0: # %entry
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
|
|
; X86-NEXT: movb $-98, 2(%edx)
|
|
; X86-NEXT: movw $-24930, (%edx) # imm = 0x9E9E
|
|
; X86-NEXT: movb $1, 2(%ecx)
|
|
; X86-NEXT: movw $257, (%ecx) # imm = 0x101
|
|
; X86-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
; X86-NEXT: psrlw $1, %xmm0
|
|
; X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
|
|
; X86-NEXT: pextrb $2, %xmm0, 2(%eax)
|
|
; X86-NEXT: pextrw $0, %xmm0, (%eax)
|
|
; X86-NEXT: retl $4
|
|
;
|
|
; X64-LABEL: rot:
|
|
; X64: # %bb.0: # %entry
|
|
; X64-NEXT: movq %rdi, %rax
|
|
; X64-NEXT: movb $-98, 2(%rsi)
|
|
; X64-NEXT: movw $-24930, (%rsi) # imm = 0x9E9E
|
|
; X64-NEXT: movb $1, 2(%rdx)
|
|
; X64-NEXT: movw $257, (%rdx) # imm = 0x101
|
|
; X64-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
; X64-NEXT: psrlw $1, %xmm0
|
|
; X64-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
|
|
; X64-NEXT: pextrb $2, %xmm0, 2(%rdi)
|
|
; X64-NEXT: pextrw $0, %xmm0, (%rdi)
|
|
; X64-NEXT: retq
|
|
entry:
|
|
%storetmp = bitcast %i8vec3pack* %X to <3 x i8>*
|
|
store <3 x i8> <i8 -98, i8 -98, i8 -98>, <3 x i8>* %storetmp
|
|
%storetmp1 = bitcast %i8vec3pack* %rot to <3 x i8>*
|
|
store <3 x i8> <i8 1, i8 1, i8 1>, <3 x i8>* %storetmp1
|
|
%tmp = load %i8vec3pack, %i8vec3pack* %X
|
|
%extractVec = extractvalue %i8vec3pack %tmp, 0
|
|
%tmp2 = load %i8vec3pack, %i8vec3pack* %rot
|
|
%extractVec3 = extractvalue %i8vec3pack %tmp2, 0
|
|
%shr = lshr <3 x i8> %extractVec, %extractVec3
|
|
%storetmp4 = bitcast %i8vec3pack* %result to <3 x i8>*
|
|
store <3 x i8> %shr, <3 x i8>* %storetmp4
|
|
ret void
|
|
}
|
|
|